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參數(shù)資料
| 型號： | 73M1903C-IMR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | LEAD FREE, QFN-32 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大小： | 487K |
| 代理商： | 73M1903C-IMR/F |
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73M1903C Data Sheet
DS_1903C_033
14
Rev. 5.0
Register01 (TEST): Address 01h
Reset State 00h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMEN
DIGLB
ANALB
INTLB
CkoutEn
RXPULL
SPOS
HC
TMEN
(0X01[7])
Test Mode Enable.
0 = Normal operation
1 = Enable test modes.
DIGLB
(0X01[6])
Digital Loop back Enable
0 = Normal operation
1 = Tie the serial bit stream from the digital transmit filter output to the digital receive filter
input.
ANALB
(0X01[5])
Analog Loop back Enable
0 = Normal operation
1 = Tie the analog output of the transmitter to the analog input of the receiver.
INTLB
(0X01[4])
Internal Loop back Enable. (Remote Analog Loop back)
0 = Normal operation
1 = Tie the digital serial bit stream from the analog receiver output to the analog transmitter
input.
CkoutEn
(0X01[3])
Clock Output Enable
1 =
Enable the CLKOUT output; This bit must be set after the FSDEn bit is set to enable
daisy chain mode.
0 =
CLKOUT tri-stated, for normal operation.
RXPULL
(0X01[2])
1 =
Pulls DC Bias to RXAP/RXAN pins, thru 100Kohm each, to VREF, to be used in
testing Rx path.
0 =
No DC Bias to RXAP/RXAN pins
SPOS
(0X01[1])
1 =
Control frames occur after one quarter of the time between data frames has elapsed.
0 =
Control frames occur half way between data frames.
HC
(0X01[0])
1 =
Control frame generation is under hardware control, bit 0 of data frames on SDIN is bit
0 of the transmit word and control frames happen automatically after every data frame.
0 =
Control frame generation is under software control, bit 0 of data frames on SDIN is a
control frame request bit and control frames happen only on request.
Register06 (REV): Address 06h
Reset State 60h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev(3:0)
FSDEn
Reserved
Rev(3:0)
(0X06[7:4]) Contain the revision ID of the 73M1903C device. The rest of this register is for
chip development purposes only and is not intended for customer use. Do not write to
reserved locations.
FSDEn
(0X06[3])
Delayed Frame Sync Enable. This bit shall be enabled if the daisy chain mode is
used.
1 = Delayed frame sync for daisy chaining of additional 73M1903C devices.
0 =
FSD tristated, for normal operation.
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