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參數資料
| 型號： | 9161A-01CW16LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 120 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | LEAD FREE, SOIC-16 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 544K |
| 代理商： | 9161A-01CW16LFT |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9161A
9161
0210I—03/21/05
Block Diagram
Dual Programmable Graphics Frequency Generator
The ICS9161A is a fully programmable graphics clock
generator. It can generate user-specified clock
frequencies using an externally generated input
reference or a single crystal. The output frequency is
programmed by entering a 24-bit digital word through
the serial port.Two fully user-programmable phase-
locked loops are offered in a single package. One PLL
is designed to drive the memory clock, while the
second drives the video clock. The outputs may be
changed on-the-fly to any desired frequency between
390 kHz and 120 MHz. The ICS9161A is ideally suited
for any design where multiple or varying frequencies
are required.
This part is ideal for graphics applications. It generates
low jitter, high speed pixel clocks. It can be used to replace
multiple, expensive high speed crystal oscillators. The
flexibility of the device allows it to generate non-standard
graphics clocks.
The ICS9161A is also ideal in disk drives. It can generate
zone clocks for constant density recording schemes. The low
profile, 16-pin SOIC or PDIP package and low jitter outputs
are especially attractive in board space critical disk drives.
The leader in the area of multiple output clocks on a single
chip, ICS has been shipping graphics frequency generators
since October, 1990, and is constantly improving the
phase-locked loop.The ICS9161A incorporates a patented
fourth generation PLL that offers the best jitter performance
available.
Pin-for-pin and function compatible with ICD2061A
Dual programmable graphics clock generator
Memory and video clocks are individually
programmable on-the-fly
Ideal for designs where multiple or varying
frequencies are required
Increased frequency resolution from optional pre-
divide by 2 on the M counter
Output enable feature available for tristating outputs
Independent clock outputs range from 390 kHz to
120 MHz for VDD >4.75V
Power-down capabilities
Low power, high speed 0.8 CMOS technology
Glitch-free transitions
Available in 16-pin, 300-mil SOIC or PDIP package
EXTCLK
EXTSEL
VCO OUTPUT
DIVIDER
R=1,2,4,8,16
32,64,128
VCO
CMOS
OUTPUT
DRIVER
MCLK
OE
VCO
DIVIDE
(N÷)
VCO OUTPUT
DIVIDER
R=1,2,4,8,16
32,64,128
VCO
REF
DIVIDE
(M÷)
MUX
CMOS
OUTPUT
DRIVER
VCLK
D14-D20
7
D0-D3
4
D11-D13
3
REF
f
D14-D20
7
D4-D10
7
D0-D3
4
D11-D13
3
24
MCLK
(D0-D20)
21
VCLK
(D0-D20)
21
REGISTERS
3
ADDRESS
INIT
ROM
POR
INIT1
INIT2
SEL0-CLK
SEL1-DATA
DECODE
LOGIC
21
DATA
CONTROL REG
XTAL
OSC
X1
X2
PD
3-TO-1
MUX
Pscale
P=2or4
REF
DIVIDE
(M÷)
D4-D10
7
VCO
DIVIDE
(N÷)
Pscale
P= 2
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