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參數(shù)資料
| 型號(hào)： | 9161A-01CW16LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 120 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | LEAD FREE, SOIC-16 |
| 文件頁(yè)數(shù)： | 13/15頁(yè) |
| 文件大小： | 544K |
| 代理商： | 9161A-01CW16LFT |
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7
ICS9161A
0210I—03/21/05
Power Management Issues
Power-down mode 1
The ICS9161A contains a mechanism to reduce the
quiescent power when stand-by operation is desired.
Power-down mode 1 is invoked by polling PD# low and
having the proper CNTL register bit set to zero. In this
mode, VCOs are shut down, the VCLK output is forced
high, and the MCLK output is set to a user-defined low
frequency value to refresh dynamic RAM.
The power-down MCLK value is determined by the following
equation:
MCLKPD = FREF/(PWRDWN register divisor value)
The power-down register divisor is determined according
to the 4-bit word programmed into the PWRDWN register
(see table below).
Power-down mode 2
When there is no need for any output during power-down,
an alternate mode is available which will completely shut
down all outputs and the reference oscillator, but still
preserves all register contents. Power-down mode 2 in
invoked by first programming the power-down bit in the
CNTL register and then pulling the PD# pin low.
The PD# pin
The PD# pin has a standard internal pull-up resistor during
normal operation. When the chip goes into power-down
mode 1 or 2, the normal pull-up resistor is dynamically
switched to a weak pull-up, which reduces power
consumption. If the PD# pin is allowed to float after it has
been
pulled
down, the weak pull-up will bring the signal high and allow
the device to resume operation.
Power-Down Register Table
s
t
i
b
N
W
D
R
W
PN
W
D
R
W
Pn
w
o
d
-
r
e
w
o
PD
P
K
L
C
M
3
P2
P1
P0
Pe
u
l
a
V
r
e
t
s
i
g
e
Rr
o
s
i
v
i
Df
(
F
E
R
)
8
1
8
1
3
.
4
1
=
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
)
t
l
u
a
f
e
d
(
8
9
A
B
C
D
E
F
a
/
n
2
3
0
3
8
2
6
2
4
2
0
2
8
1
6
1
4
1
2
1
0
1
8
6
4
a
/
n
z
H
k
4
.
7
4
z
H
k
3
.
7
4
z
H
k
4
.
1
5
z
H
k
7
.
0
5
z
H
k
6
.
6
9
5
z
H
k
8
.
0
5
6
z
H
k
9
.
5
1
7
z
H
k
5
.
5
9
7
z
H
k
9
.
4
9
8
z
H
M
2
0
.
1
z
H
M
9
1
.
1
z
H
M
3
4
.
1
z
H
M
9
7
.
1
z
H
M
9
3
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2
z
H
M
8
5
.
3
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