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參數(shù)資料
| 型號： | 9179YF-03LF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9179 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 273K |
| 代理商： | 9179YF-03LF-T |
3
ICS9179-03
0258K 12/15/08
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for OUTPUT (0:9).
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
OUTPUT (0:9)
These Output Clocks are use to drive Dynamic RAM’s and
are low skew copies of the CPU Clocks. The voltage swing of
the OUTPUTs output is controlled by the supply voltage
that is applied to VDD of the device, operates at 3.3 volts.
I
2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I
2C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I
2C specification
in Philips I
2C Peripherals Data Handbook (1996) should be
followed.
BUF_IN
Input for Fanout buffers (OUTPUT 0:9).
OE
OE tristates all outputs when held low.
VDD1
This is the power supply to I
2C circuitry.
Technical Pin Function Descriptions
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