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參數資料
| 型號： | 9214DGLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9214 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.173 INCH, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-28 |
| 文件頁數： | 13/18頁 |
| 文件大小： | 310K |
| 代理商： | 9214DGLF-T |
4
Integrated
Circuit
Systems, Inc.
ICS9214
0809E—11/17/06
SMB Table: Output Control Register
Control
Function
Bit 7
Test Mode
Reserved for Vendor
RW
0
Bit 6
MULT2
Multiplier Select
RW
0
Bit 5
MULT1
Multiplier Select
RW
0
Bit 4
MULT0
Multiplier Select
RW
1
Bit 3
ODCLK_T/C0
Output Control
RW
1
Bit 2
ODCLK_T/C1
Output Control
RW
1
Bit 1
ODCLK_T/C2
Output Control
RW
1
Bit 0
ODCLK_T/C3
Output Control
RW
1
Disable = Output in high-impedance state
Enable = Output is switching
SMB Table: Frequency Multiplier Control Register
Control
Function
Bit 7
Reserved
RW
0
Bit 6
Reserved
RW
0
Bit 5
Reserved
RW
0
Bit 4
Reserved
RW
0
Bit 3
Reserved
RW
0
Bit 2
Reserved
RW
0
Bit 1
Reserved
RW
0
Bit 0
Test Mode
Reserved for Vendor
RW
0
SMB Table: Revision & Vendor ID Register
Control
Function
Bit 7
RID4
R
X
Bit 6
RID3
R
X
Bit 5
RID2
R
X
Bit 4
RID1
R
X
Bit 3
RID0
R
X
Bit 2
VID2
R
0
Bit 1
VID1
R
0
Bit 0
VID0
R
1
NOTES:
1. PWD = Power Up Default
Disable
Enable
--
Vendor ID
-
--
Revision ID
-
--
-
--
01
See Table 2.
PWD
1
PWD
-
--
Byte 2
Pin #
Name
Type
-
Byte 0
Pin #
Name
Type
Disable
Enable
01
-
Byte 1
Pin #
-
27,26
24,23
20,19
17,16
-
--
Name
Type
0
1
--
-
--
-
--
-
--
PWD
Disable
Enable
Disable
Enable
Disable
Enable
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