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參數資料
| 型號： | 9214DGLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9214 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.173 INCH, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-28 |
| 文件頁數： | 3/18頁 |
| 文件大小： | 310K |
| 代理商： | 9214DGLF-T |
11
Integrated
Circuit
Systems, Inc.
ICS9214
0809E—11/17/06
Figure 1. Differential and single-ended reference clock inputs
Clock Output Drivers
Figure 2 shows the clock driver equivalent circuit. The differential driver produces a specified voltage swing on the channel
by switching the currents going into ODCLK_T and ODCLK_C. The external resistor RRC at the IREFY pin sets the maximum
current. The minimum current is zero.
The voltage at the IREFY pin, VIREFY, is by design equal to 1 V nominally, and the driver current is seven times the current
flowing through RRC. So, the output low current can be estimated as IOL = 7/ RRC.
The driver output characteristics are defined together with the external resistors, R1, R2, and R3. The output clock signals are
specified at the measurement points indicated in Figure 2. Table 5 shows example values for the resistors.
R1, R2, and R3 and the clock driver output impedance, ZOUT, must match the impedance of the channel, ZCH , to minimize
secondary reflections. ZOUT is specified as 1000 Ohms, minimum to accomplish this. The effective impedance can be
estimated by:
(1000R1/(1000+R1)+R2) R3/(1000R1/(1000+R1)+R2+R3)
Pull-up resistor RT terminates the transmission line at the load to minimize clock signal reflection signal reflections. Table 5
shows the resistor values for establishing and effective source termination impedance of 49.2 Ohms to match a 50 Ohm
channel. The termination voltages are 2.5 V for VTS and 1.2 V for VT. The resistor values R1 = 38.3 Ohms, R2 = 19.1 Ohms, R3
= 54.9 Ohms and RRC = 200 Ohms can be used to match a 28 Ohm channel.
Table 5. Example Resistor Values and Termination Voltages for a 50 Ohm Channel
1
Symbol
Parameter
Value
Tolerance
Unit
R1
Termination resistor
39.2
+/- 1%
R2
Termination resistor
66.5
+/- 1%
R3
Termination resistor
93.1
+/- 1%
RT
Termination resistor
49.9
+/- 1%
RRC
Swing control resistor
200
+/- 1%
VTS
Source termination voltage
2.5
+/-5%
V
VT
Termination voltage
1.2
+/-5%
V
Notes:
1 A different set of resistors is used in Figure 2 when testing
for maximum output current of the clock driver (IOLABS).
These resistors are: R1 = 34, R2 = 31.8, R3 = 48.7,
RT=28, RRC = 147
VTH
Inp ut
XDR
CLK_INC
CLK_INT
a. Differential input
b. Single-ended input
Clock Generator
Supply Voltage
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