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| 型號(hào)： | 935261222557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, SOT-319, QFP-64 |
| 文件頁(yè)數(shù)： | 8/36頁(yè) |
| 文件大小： | 203K |
| 代理商： | 935261222557 |
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1999 Jun 14
16
Philips Semiconductors
Preliminary specication
ATSC 8-VSB demodulator and decoder
TDA8960
Table 7
TAP external interface
SIGNAL
TYPE
DESCRIPTION
TMS
I
test mode select
TCK
I
test clock
TDI
I
test data input
TDO
O
test data output
TRST
I
test asynchronous reset
OPERATION
The TAP controller is a finite state machine. It selects a
JTAG instruction or a data register to store the input based
on the TMS signal, receives instructions and data on the
TDI pin, executes the instruction when triggered by TMS,
and shifts data out of TDO.
TCK provides the clock signal for the test logic required by
the standard. TCK is asynchronous to the system clock.
Stored devices in the JTAG controller must retain their
state indefinitely when TCK is stopped at logic 0.
The signal received at TMS is decoded by the TAP
controller to control test functions. The logic is required to
sample TMS at the rising edge of TCK.
Serial test instructions and test data are received at TDI.
The TDI signal is required to be sampled at the rising edge
of TCK. When test data is shifted from TDI to TDO, the
data must appear without inversion at TDO after a number
of rising and falling edges of TCK, determined by the
length of the instruction or test data register selected.
TDO is the serial output for test instructions and data from
the TAP controller. Changes in the state of TDO must
occur after the falling edge of TCK. This is because
devices connected to TDO are required to sample TDO at
the rising edge of TCK. The TDO driver must be in an
inactive state (i.e. TDO line must be flat) except when the
scanning of data is in progress.
I2C-bus interface
The I2C-bus interface is used to write control information to
and read low-speed diagnostic information from the
TDA8960. The key features of the I2C-bus interface are:
I2C-bus data rate up to 400 kbits/s
Support for only 7-bit addressing and the possibility of
modifying the slave address externally.
A typical system using the I2C-bus interface is illustrated in
Fig.7. The TDA8960 is connected as a slave to a master
through SCL and SDA. Note that the bus has one pull-up
resistor for each of the clock and data lines.
EXTERNAL INTERFACE
The I2C-bus interface consists of four signals as shown in
Table 8.
Table 8
I2C-bus external interface
The TDA8960 has 3.3 V I/O and I2C-bus pins. Therefore,
in a complete system some circuitry might be necessary to
allow ICs with different supply voltages to communicate
and be controlled. This has been described in an
application report available from Philips Semiconductors
(application report
“AN97055”, issued 1997 Aug 04).
SIGNAL
TYPE
DESCRIPTION
SDA
I/O
I2C-bus serial data
SCL
I
I2C-bus clock
A0
I
I2C-bus slave address bit 0
A1
I
I2C-bus slave address bit 1
Fig.7 Typical I2C-bus system implementation.
handbook, halfpage
MGR606
TDA8960
I2C-BUS
MASTER
VDD
Rpu
SCL
SDA
Rpu
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