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參數資料
| 型號： | 935261790112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | 5.30 MM, PLASTIC, SSOP-28 |
| 文件頁數： | 5/31頁 |
| 文件大小： | 199K |
| 代理商： | 935261790112 |
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2000 Feb 04
13
Philips Semiconductors
Preliminary specication
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
handbook, full pagewidth
tstp(L3)
address
L3DATA
L3CLOCK
L3MODE
address
data byte #1
data byte #2
MGL725
Fig.6 Multibyte data transfer.
L3 interface registers
When the data transfer of type ‘status’ is selected, the features system clock frequency, data input format and DC filter
can be controlled.
Table 14 Data transfer of type ‘status’
When the data transfer of type ‘data’ is selected, the features volume, bass boost, treble, de-emphasis, mute, mode and
power control can be controlled.
Table 15 Data transfer of type ‘data’
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
SC1
SC0
IF2
IF1
IF0
DC
SC = system clock frequency (2 bits); see Table 16
IF = data input format (3 bits); see Table 17
DC = DC lter (1 bit); see Table 18
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
VC5
VC4
VC3
VC2
VC1
VC0
VC = volume control (6 bits); see Table 19
0
1
BB3
BB2
BB1
BB0
TR1
TR0
BB = bass boost (4 bits); see Table 20
TR = treble (2 bits); see Table 21
1
0
DE1
DE0
MT
M1
M0
DE = de-emphasis (2 bits); see Table 22
MT = mute (1 bit); see Table 23
M = lter mode (2 bits); see Table 24
110000
PC1
PC0
PC = power control (2 bits); see Table 25
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