
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 13: FGPO: Fast General Purpose Output
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
13-8
The THRESHn_REACHED condition is ‘sticky’ and can only be cleared by software
writing a ‘1’ to the FGPO_IR_CLR.THRESHn_REACHED_ACK bit.
Remark: This interrupt is generated when the FGPO Engine finishes reading the last
sample from the threshold record/message number from main memory and NOT
when the last sample from the threshold record/message number is output.
2.7.3
UNDERRUN Interrupt
If software fails to assign a new buffer (update FGPO_BASEn register) and perform
an interrupt acknowledge (clear BUFnDONE interrupt) before both buffers are done,
the interrupt event FGPO_IR_STATUS.UNDERRUN will be set and the output of
samples will stop.
This happens when the FGPO switches to a buffer for which:
– a buffer done event has occurred and
– the buffer done interrupt has not been acknowledged and
– the corresponding enable bit is set and
– a new record or message start event has arrived
Output continues upon receipt of either BUF1DONE_ACK or BUF2DONE_ACK or
UNDERRUN condition is ‘sticky’ and can only be cleared by software writing a ‘1’ to
the UNDERRUN_ACK bit.
2.7.4
MBE Interrupt
A Memory Bandwidth Error (MBE) interrupt is generated when no data samples care
available during a record or message transfer. During the time MBE state exists the
last valid data sample will be output on the fgpo_data pins. Therefore one or more
data samples will be added to the message until the adapter FIFO contains valid data
samples. Then sample output resumes. For example if FGPO is set to send a
message with 6 samples and an MBE occurs before D3 is output, i.e. D3 has not yet