
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 19: Memory Based Scaler
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
19-6
2.4 General Operations
This section provides the details on how the MBS functions. A description of each
functional group is provided.
2.4.1
Task Control
Since the MBS is capable of processing several video streams in sequence, a
pipelining mechanism is implemented for scaling a sequence of tasks. A task is
described by a data structure stored in memory. Writing the base address of this task
into the Task FIFO schedules the task to be executed after the completion
(processing) of the previously-scheduled tasks.
In addition to the task list in the FIFO, each Task structure in memory can consist of a
linked list of sub tasks that will be executed in sequence (
e.g., HD scaling task via
partitioning). The software scheduling algorithm is responsible for preventing the Task
FIFO from overowing. An interrupt can be generated, once the last task in the FIFO
gets executed, in order to request new tasks from the scheduler. Other interrupt
events also exist and they aid in the task of keeping the task FIFO lled and avoiding
overow in the four available FIFO slots.
Table 3: De-Interlacing Mode Maximum Filter Lengths
Input Format
EDDI
MSA 2 Field (Y:UV Taps)
MSA 3 Field (Y:UV Taps)
Median (Y:UV Taps)
4:2:0 or 4:2:2 planar
Yes
6:6
Not supported
6:6
4:2:0 or 4:2:2 semi-planar
Yes
6:6
6:61
6:6
4:2:2 single plane
No
Not supported
6:6
1Only supported in Vertical-First mode
Figure 5:
Task FIFO and Linked List
Base 1
Base 2
empty
Sub-Task Base
Descriptor #1 start
...
Descriptor #2 start
...
Descriptor #2 end
Sub-Task start
...
Descriptor #1 end
Memory
FIFO in
FIFO out
four
entries