
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
23-3
2.2 Functional Block Diagram
Figure 2 shows a more detailed block diagram of the main internal units of the
LAN100. Primary components of the LAN100, shown as blocks outlined in black, are
described below. The Transmit Datapath and Receive Datapath are shown with
unoutlined background colors.
The registers provide MMIO acces to the LAN100. They interface to the transmit and
receive data-paths, and to the MII Interface.
The MII Interface connects the LAN100 to the off-chip PHY.
The Transmit Datapath has two transmit DMA managers, DMA0 and DMA1, which
read descriptors and data from memory and write status to memory. In real-time
mode, DMA0 can be used to handle real-time transmissions and DMA1 can be used
to handle non-real-time transmissions. In Quality-of-Service (QoS) mode, DMA0 has
the lowest priority and DMA1 has the highest priority.
Transmission from both of the transmit DMA managers is mediated by arbitration
logic, including:
Multiplexers to select one of the transmit DMA managers
Transmit Retry module to handle Ethernet retry and abort conditions
Transmit Flow Control module to insert Ethernet pause frames where needed.
Figure 2:
LAN100 Functional Block Diagram
LAN100
MIIM
(R)MII Tx
(R)MMI Rx
Device Registers
MMIO
Descriptors
Data
Status
Descriptors
Data
Status
Descriptors
Data
Status
Rx Filter
Rx
Parser
Rx DMA
Tx DMA1
Tx DMA0
Time-stamp and
QoS Arbiter
Tx Flow Control
Tx Retry
MII
Interface
Tx Data
Tx Status
Rx Buffer
Control
Abort
Pass or block packets
Buffer and abort logic
Pause frame insertion
Receive Datapath
Transmit Datapath
Rx
Parser
Rx DMA
Tx DMA1
Tx DMA0
Tx Retry
Module