
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 25: I2C Interface
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
25-8
3.1 Register Tables
Bit 7: AA Address Acknowledge
If the AA ag is set, an acknowledge (low level to SDA) will be returned during the
acknowledge clock pulse on the SCL line when:
The “own slave address” has been received.
The general call address has been received while the general call bit (GC) in the
ADR register is set.
A data byte has been received while IIC module is in the master receiver mode.
A data byte has been received while IIC module is in the addressed slave
receiver mode.
Table 2: IIC Registers
Bit
Symbol
Acces
s
Value
Description
Offset 0x04 5000
I2C CONTROL
31:8
Unused
-
Ignore upon read. Write as zeroes.
7
AA
R/W
0
IIC acknowledge bit
0 = Acknowledge not returned during acknowledge clock pulse
1 = Acknowledge returned during acknowledge clock pulse
6
EN
R/W
0
IIC enable bit
0 = Disable IIC module
1 = Enable IIC module
5
STA
R/W
0
IIC start bit
0 = Slave mode, accept transactions
1 = Master mode, generate start condition if bus is free
4
STO
R
0
IIC stop bit
0 = Slave mode, accept transactions
1 = Generate stop condition on I2C bus when IIC module is
master.
3
Unused
-
Ignore upon read. Write as zeroes.
2:0
CR
R/W
100
These three bits determine the serial clock frequency when
IIC module is in master mode. This eld shall be changed
only when EN bit is 0. The IIC Clock is divided as follows to
achieve the desired frequency. The table assumes the IIC module
receives a 24 MHz clock from the Clock module.
0: 60 -> 400 KHz
1: 80 -> 300 KHz
2: 120 -> 200 KHz
3: 160 -> 150 KHz
4: 240 -> 100 KHz
5: 320 -> 75 KHz
6: 480 -> 50 KHz
7: 960 -> 25 KHz