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參數資料
| 型號： | 9704-11 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3.0 GHz Integer-N PLL for Rad Hard Apllications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁數： | 7/10頁 |
| 文件大?。?/td> | 247K |
| 代理商： | 9704-11 |
Product Specification
PE9704
Page 6 of 10
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0083-03
│ UltraCMOS RFIC Solutions
Functional Description
The PE9704 consists of a prescaler, counters, a
phase detector, and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via a serial bus or
hardwired directly to the pins. There are also
various operational and test modes and a lock
detect output.
Main Counter Chain
Normal Operating Mode
Setting the PB control bit “low” enables the ÷10/11
prescaler. The main counter chain then divides
the RF input frequency (FIN) by an integer derived
from the values in the “M” and “A” counters.
In this mode, the output from the main counter
chain (fp) is related to the VCO frequency (FIN) by
the following equation:
fp = FIN / [10 x (M + 1) + A]
(1)
where A
≤ M + 1, 1 ≤ M ≤ 511
When the loop is locked, FIN is related to the
reference frequency (FR) by the following
equation:
FIN = [10 x (M + 1) + A] x (FR / (R+1))
(2)
where A
≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that FIN
must be greater than or equal to 90 x (FR / (R+1))
to obtain contiguous channels. The A counter can
accept values as high as 15, but in typical
operation it will cycle from 0 to 9 between
increments in M.
Programming the M counter with the minimum
allowed value of “1” will result in a minimum M
counter divide ratio of “2”.
Prescaler Bypass Mode
Setting the enhancement register bit PB “high”
allows FIN to bypass the ÷10/11 prescaler. In
this mode, the prescaler and A counter are
powered down, and the input VCO frequency is
divided by the M counter directly. This mode is
only available when using the serial port to set
the frequency control bits. The following
equation relates FIN to the reference frequency
FR:
FIN = (M + 1) x (FR / (R+1)) )
(3)
where 1 ≤ M ≤ 511
Reference Counter
The reference counter chain divides the
reference frequency FR down to the phase
detector comparison frequency fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the
following equation:
fc = FR / (R + 1)
(4)
where 0 ≤ R ≤ 63
Note that programming R with “0” will pass the
reference frequency (FR) directly to the phase
detector.
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| 970420361 | 功能描述:Hex Spacer Threaded M3x0.5 Steel 1.654" (42.00mm) 制造商:wurth electronics inc 系列:WA-SSTII 零件狀態:新產品 類型:六角襯墊 有絲/無絲:有螺紋 公母:母頭，母頭 螺釘，螺紋規格:M3x0.5 直徑 - 內部:- 直徑 - 外部:0.236"（6.00mm） 六角形 板間高度:1.654"（42.00mm） 長度 - 總:1.654"（42.00mm） 特性:表面貼裝型 材料:鋼 鍍層:鋅 顏色:- 重量:- 標準包裝:750 |
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