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參數(shù)資料
| 型號(hào)： | 9763-01 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, CQCC68 |
| 封裝： | CERAMIC, QFJ-68 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大小： | 351K |
| 代理商： | 9763-01 |
Product Specification
PE9763
Page 9 of 15
Document No. 70-0140-02
│ www.psemi.com
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Main Counter Chain
Normal Operating Mode
Setting the Pre_en control bit “l(fā)ow” enables the
÷10/11 prescaler. The main counter chain then
divides the RF input frequency (Fin) by an integer
or fractional number derived from the values in the
“M”, “A” counters and the DSM input word K. The
accumulator size is 18 bit, so the fractional value
is fixed from the ratio K/218. There is an additional
bit in the DSM that acts like an extra bit (19th bit).
This bit is enabled by asserting the pin
RAND_SEL to “high”. Enabling this bit has the
benefit of reducing the spurious levels. However,
a small frequency offset will occur. This positive
frequency offset is calculated with the following
equation.
foffset = (fr / (R + 1)) / 2
19
(1)
All of the following equations do not take into
account of this frequency offset. If this offset is
important to a specific frequency plan, appropriate
account needs to be taken.
In the normal mode, the output from the main
counter chain (fp) is related to the VCO frequency
(Fin) by the following equation:
fp = Fin / [10 x (M + 1) + A + K/2
18]
(2)
where A
≤ M + 1, 1 ≤ M ≤ 511
When the loop is locked, Fin is related to the
reference frequency (fr) by the following equation:
Fin = [10 x (M + 1) + A + K/2
18] x (f
r / (R+1))
(3)
where A
≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. The A counter can
accept values as high as 15, but in typical
operation it will cycle from 0 to 9 between
increments in M.
Programming the M counter with the minimum
allowed value of “1” will result in a minimum M
counter divide ratio of “2”.
Prescaler Bypass Mode (*)
Setting the frequency control register bit Pre_en
“high” allows Fin to bypass the ÷10/11 prescaler.
In this mode, the prescaler and A counter are
powered down, and the input VCO frequency is
divided by the M counter directly. The following
equation relates Fin to the reference frequency fr:
Fin = (M + 1) x (fr / (R+1))
(4)
where 1
≤ M ≤ 511
(*) Only integer mode
In frequency bypass mode, neither A counter or K
counter is used. Therefore, only integer-N
operation is possible.
Reference Counter
The reference counter chain divides the reference
frequency fr down to the phase detector
comparison frequency fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
fc = fr / (R + 1)
(5)
where 0
≤ R ≤ 63
Note that programming R with “0” will pass the
reference frequency (fr) directly to the phase
detector.
Register Programming
Serial Interface Mode
While the E_WR input is “l(fā)ow” and the S_WR
input is “l(fā)ow”, serial input data (Sdata input), B0 to
B20, are clocked serially into the primary register
on the rising edge of Sclk, MSB (B0) first. The LSB
is used as address bit. When “0”, the contents
from the primary register are transferred into the
secondary register on the rising edge of either
S_WR according to the timing diagrams shown in
Figure 4. When “1”, data is transferred to the
auxiliary register according to the same timing
diagram. The secondary register is used to
program the various counters, while the auxiliary
register is used to program the DSM.
Data are transferred to the counters as shown in
Table 8 on page 10.
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