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參數資料
| 型號： | 9763-11 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, CQCC68 |
| 封裝： | CERAMIC, QFJ-68 |
| 文件頁數： | 14/15頁 |
| 文件大小： | 351K |
| 代理商： | 9763-11 |
Product Specification
PE9763
Page 8 of 15
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0140-02
│ UltraCMOS RFIC Solutions
Functional Description
The PE9763 consists of counters, a prescaler, an
18-bit delta-sigma modulator (DSM), a phase
detector and a charge pump. The dual modulus
prescaler divides the VCO frequency by either 10
or 11, depending on the value of the modulus
select. Counters “R” and “M” divide the reference
and prescaler output, respectively, by integer
values stored in a 20-bit register.
An additional
counter (“A”) is used in the modulus select logic.
The DSM modulates the “A” counter outputs in
order to achieve the desired fractional step.
The phase-frequency detector generates up and
down frequency control signals. These signals can
be configured to drive a tri-state charge pump.
Data is written into the internal registers via the
three wire serial bus. There are also various
operational and test modes and a lock detect
output
Figure 3. Functional Block Diagram
Control
Logic
Modulus
Select
10/11
Prescaler
M Counter
(9-bit)
R Counter
(6-bit)
Phase
Detector
R(5:0)
M(8:0)
A(3:0)
Sdata
Control
Pins
fr
Fin
2 k
LD
Cext
Fin
fc
fp
DSM
+
Logic
Charge
Pump
Icp
PD_U
PD_D
K(17:0)
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