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參數資料
| 型號： | 9763-11 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, CQCC68 |
| 封裝： | CERAMIC, QFJ-68 |
| 文件頁數： | 3/15頁 |
| 文件大小： | 351K |
| 代理商： | 9763-11 |
Product Specification
PE9763
Page 11 of 15
Document No. 70-0140-02
│ www.psemi.com
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Enhancement Register
Figure 4. Serial Interface Mode Timing Diagram
t
DHLD
t
DSU
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
t
EC
t
CE
E_WR
Sdata
Sclk
S_WR
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 10. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserve **
Reserved.
Bit 1
Reserve **
Reserved.
Bit 2
fp output
Drives the M counter output onto the Dout output.
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
fc output
Drives the reference counter output onto the Dout output.
Bit 7
LD Disable
Disables the LD pin for quieter operation.
** Program to 0
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