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參數(shù)資料
| 型號： | 9LP525BF-2LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 226K |
| 代理商： | 9LP525BF-2LFT |
ICS9LP525-2
IDT PC MAIN CLOCK
1397—11/08/10
56-pin CK505 for Intel Desktop Systems
1
DATASHEET
Pin Configuration
Recommended Application:
CK505 clock, 56-pin Intel Yellow Cover part
Output Features:
2 - CPU differential low power push-pull pairs
7- SRC differential low power push-pull pairs
1 - CPU/SRC selectable differential low power push-pull pair
1 - SRC/DOT selectable differential low power push-pull pair
5 - PCI, 33MHz
1 - PCI_F, 33MHz free running
1 - USB, 48MHz
1 - REF, 14.318MHz
Key Specifications:
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter < 125ps
PCI outputs cycle-cycle jitter < 250ps
+/- 100ppm frequency accuracy on all outputs
SRC are PCIe Gen2 compliant
PCI0/CR#_A 1
56 SCLK
VDDPCI 2
55 SDATA
PCI1/CR#_B 3
54 REF0/FSLC/TEST_SEL
PCI2/TME 4
53 VDDREF
PCI3/CFG0 5
52 X1
PCI4/SRC5_EN 6
51 X2
PCI_F5/ITP_EN 7
50 GNDREF
GNDPCI 8
49 FSLB/TEST_MODE
VDD48 9
48 CK_PWRGD/PD#
USB_48MHz/FSLA 10
47 VDDCPU
GND48 11
46 CPUT0
VDD96_IO 12
45 CPUC0
DOTT_96/SRCT0 13
44 GNDCPU
DOTC_96/SRCC0 14
43 CPUT1_F
GND 15
42 CPUC1_F
VDD 16
41 VDDCPU_IO
SRCT1/SE1 17
40 VOUT
SRCC1/SE2 18
39 CPUT2_ITP/SRCT8
GND 19
38 CPUC2_ITP/SRCC8
VDDPLL3_IO 20
37 VDDSRC_IO
SRCT2/SATAT 21
36 SRCT7/CR#_F
SRCC2/SATAC 22
35 SRCC7/CR#_E
GNDSRC 23
34 GNDSRC
SRCT3/CR#_C 24
33 SRCT6
SRCC3/CR#_D 25
32 SRCC6
VDDSRC_IO 26
31 VDDSRC
SRCT4 27
30 PCI_STOP#/SRCT5
SRCC4 28
29 CPU_STOP#/SRCC5
56-SSOP & TSSOP
9
L
P
5
2
5
-2
Features/Benefits:
Supports spread spectrum modulation, default is 0.5%
down spread
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Selectable SRC differential push-pull pair/two single
ended outputs
Table 1: CPU Frequency Select Table
FSLC
2
B0b7
FSLB
1
B0b6
FSLA
1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0
266.66
0
1
133.33
0
1
0
200.00
0
1
166.66
1
0
333.33
1
0
1
100.00
1
0
400.00
1
1. FS
LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
LC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Reserved
100.00
33.33 14.318 48.00 96.00
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9LP525BG-2LF | 功能描述:時鐘合成器/抖動清除器 CK505 PCIe Gen2 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LP525BG-2LFT | 功能描述:時鐘合成器/抖動清除器 CK505 PCIe Gen2 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LPC01781 | 制造商:Denon 功能描述:BUTTON POWERAVR-600 |
| 9LPH02002 | 制造商:Denon 功能描述:DISPLAY SHEETD-C30 |
| 9LPH02481 | 制造商:Denon 功能描述:F/PANELD-C30 |
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