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參數資料
| 型號： | A40MX04-FPL68 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數： | 27/124頁 |
| 文件大小： | 3142K |
| 代理商： | A40MX04-FPL68 |
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FPGA Families 40MX and 42MX
3- 2
v6.1
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
5.1
(continued)
In the 100-Pin PQFP table, the following pins changed:
Pin 64 (42MX09 and 42MX16) has changed to LP
In the 160-Pin PQFP table, the following pins changed:
Pin 61 (42MX09, 42MX16, and 42MX64) has changed to LP
In the 208-Pin PQFP table, the following pins changed:
Pin 129 (42MX09, 42MX16, and 42MX64) has changed to LP
Pin 198 (42MX09) has changed to I/O
The n the 240-Pin PQFP table, the following pins changed:
Pin 91 (42MX36) has changed to LP
In the 100-Pin VQFP Package table, the following pins changed:
Pin 62 (42MX09 and 42MX16) has changed to LP
In the 176-Pin TQFP table, the following pins changed:
Pin 109 (42MX09 and 42MX16) has changed to LP
In the 272-Pin PBGA table, the following pins changed:
Pin K20 (42MX36) has changed to LP
v5.0
The "Low Power Mode" section was updated.
Footnote 8 in the Table 9 5V TTL Electrical Specifications was updated.
Footnote 8 in the Table 13 3.3V LVTTL Electrical Specifications was updated.
v4.0.1
Because the changes in this data sheet are extensive and technical in nature, this should be viewed
as a new document. Please read it as you would a data sheet that is published for the first time.
ALL
Note that the “Package Characteristics and Mechanical Drawings” section has been eliminated
from the data sheet. The mechanical drawings are now contained in a separate document,
“Package Characteristics and Mechanical Drawings,” available on the Actel web site.
Previous version
Changes in current version (v 6. 1 )
Page
相關PDF資料 |
PDF描述 |
|---|---|
| A40MX04-FPL84X79 | FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84 |
| A40MX04-FPL84 | FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84 |
| A40MX04-FPQ100X79 | FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP100 |
| A40MX04-FPQ100 | FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP100 |
| A40MX04-FVQ80X79 | FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP80 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| A40MX04-FPL68I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A40MX04-FPL68M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A40MX04-FPL84 | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:MX 標準包裝:152 系列:IGLOO PLUS LAB/CLB數:- 邏輯元件/單元數:792 RAM 位總計:- 輸入/輸出數:120 門數:30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14） |
| A40MX04-FPL84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A40MX04-FPL84M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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