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參數資料
型號： A40MX04-FVQ80X79
元件分類： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP80
封裝： 1 MM HEIGHT, PLASTIC, VQFP-80
文件頁數： 80/124頁
文件大小： 3142K
代理商： A40MX04-FVQ80X79
40MX and 42MX FPGA Families
v6.1
1-53
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.8
2.17
3.0
ns
tINYL
Pad-to-Y LOW
1.2
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
1.8
2.0
2.3
2.7
3.7
ns
tINGL
G to Y LOW
1.8
2.0
2.3
2.7
3.7
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
2.8
3.2
3.6
4.2
5.9
ns
tIRD2
FO=2 Routing Delay
3.2
3.5
4.0
4.7
6.6
ns
tIRD3
FO=3 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD4
FO=4 Routing Delay
3.9
4.3
4.9
5.7
8.0
ns
tIRD8
FO=8 Routing Delay
5.2
5.8
6.6
7.7
10.8
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
4.1
4.5
5.0
5.1
5.6
6.0
6.7
8.4
9.3
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
5.0
5.4
5.5
6.0
6.2
6.8
7.3
8.0
10.2
11.2
ns
tPWH
Minimum
Pulse
Width HIGH
FO = 32
FO = 256
1.7
1.9
2.1
2.3
2.5
2.7
3.5
3.8
ns
tPWL
Minimum
Pulse
Width LOW
FO = 32
FO = 256
1.7
1.9
2.1
2.3
2.5
2.7
3.5
3.8
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
0.4
0.5
0.6
0.9
ns
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 256
0.0
ns
tHEXT
Input Latch External
Hold
FO = 32
FO = 256
3.3
3.7
4.1
4.2
4.6
4.9
5.5
6.9
7.6
ns
tP
Minimum Period
FO = 32
FO = 256
5.6
6.1
6.2
6.8
6.7
7.4
7.8
8.5
12.9
14.2
ns
fMAX
Maximum
Frequency
FO = 32
FO = 256
177
161
146
148
135
129
117
77
70
MHz
Table 33
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
PDF描述
A40MX04-FVQ80 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP80
A40MX04-PL44IX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44I FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44MX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44M FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
相關代理商/技術參數
參數描述
A40MX04-FVQG80 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:MX 標準包裝:152 系列:IGLOO PLUS LAB/CLB數:- 邏輯元件/單元數:792 RAM 位總計:- 輸入/輸出數:120 門數:30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14）
A40MX04-PL100 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A40MX04-PL100ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A40MX04-PL100I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A40MX04-PL100M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
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