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參數(shù)資料
型號(hào): AD7621AST
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC
中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝: MO-026-BBC, LQFP-48
文件頁數(shù): 15/26頁
文件大小: 265K
代理商: AD7621AST
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
–15–
CIRCUIT INFORMATION
The AD7621 is a very fast, low-power, single-supply,
precise 16-bit analog-to-digital converter (ADC) using
successive approximation architecture.
The AD7621 features different modes to optimize perfor-
mances according to the applications.
In Warp mode, the AD7621 is capable of converting
3,000,000 samples per second (3 MSPS).
The AD7621 provides the user with an on-chip
track/hold, successive approximation ADC that does not
exhibit any pipeline or latency, making it ideal for mul-
tiple multiplexed channel applications.
The AD7621 can be operated from a single 2.5 V supply
and be interfaced to either 5 V or 3.3 V or 2.5 V digital
logic. It is housed in a 48-lead LQFP or a tiny LFCSP
packages that combines space savings and allows flexible
configurations as either serial or parallel interface. The
AD7621 is pin-to-pin-compatible with the AD7674.
CONVERTER OPERATION
The AD7621 is a successive approximation analog-to-
digital converter based on a charge redistribution DAC.
Figure 3 shows the simplified schematic of the ADC.
The capacitive DAC consists of two identical arrays of 16
binary weighted capacitors which are connected to the two
comparator inputs.
During the acquisition phase, terminals of the array tied to
the comparator’s input are connected to AGND via SW
+
and SW
-
. All independent switches are connected to the
analog inputs. Thus, the capacitor arrays are used as sam-
pling capacitors and acquire the analog signal on IN+ and
IN- inputs. When the acquisition phase is complete and
the
CNVST
input goes low, a conversion phase is initi-
ated. When the conversion phase begins, SW
+
and SW
-
are
opened first. The two capacitor arrays are then discon-
SW
+
MSB
32,768C
16,384C
4C
2C
C
C
IN+
LSB
COMP
SW
-
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNVST
REF
REFGND
MSB
32,768C
16,384C
4C
2C
C
C
IN -
LSB
Figure 3. ADC Simplified Schematic
nected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between the in-
puts IN+ and IN- captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each
element of the capacitor array between REFGND or REF,
the comparator input varies by binary weighted voltage
steps (V
REF
/2, V
REF
/4 . . . V
REF
/65536). The control logic
toggles these switches, starting with the MSB first, in
order to bring the comparator back into a balanced condi-
tion. After the completion of this process, the control
logic generates the ADC output code and brings BUSY
output low.
Modes of Operation
The AD7621 features three modes of operations, Warp,
Normal, and Impulse. Each of these modes is more suit-
able for specific applications.
The Warp mode allows the fastest conversion rate up to
3 MSPS. However, in this mode, and this mode only, the
full specified accuracy is guaranteed only when the time
between conversion does not exceed 1 ms. If the time be-
tween two consecutive conversions is longer than 1 ms, for
instance, after power-up, the first conversion result should
be ignored. This mode makes the AD7621 ideal for appli-
cations where fast sample rate are required.
The normal mode is the fastest mode (2 MSPS) without
any limitation about the time between conversions. This
mode makes the AD7621 ideal for asynchronous appli-
cations such as data acquisition systems, where both high
accuracy and fast sample rate are required.
The impulse mode, the lowest power dissipation mode,
allows power saving between conversions. The maximum
throughput in this mode is 1.25 MSPS. This feature
makes the AD7621 ideal for battery-powered applications.
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