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參數資料
| 型號： | AD7621AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MO-026-BBC, LQFP-48 |
| 文件頁數： | 20/26頁 |
| 文件大小： | 265K |
| 代理商： | AD7621AST |
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
–20–
CONVERSION CONTROL
Figure 12 shows the detailed timing diagrams of the con-
version process. The AD7621 is controlled by the signal
CNVST
which initiates conversion. Once initiated, it
cannot be restarted or aborted, even by the power-down
input PD, until the conversion is complete. The
CNVST
signal operates independently of
CS
and
RD
signals.
CNVST
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7
t8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 12. Basic Conversion Timing
Although
CNVST
is a digital signal, it should be de-
signed with this special care with fast, clean edges and
levels, with minimum overshoot and undershoot or ring-
ing.
For applications where the SNR is critical, the
CNVST
signal should have a very low jitter. Some solutions to
achieve that are to use a dedicated oscillator for
CNVST
generation or, at least, to clock it with a high frequency
low jitter clock as shown in Figure 5.
In impulse mode, conversions can be automatically initi-
ated. If
CNVST
is held low when BUSY is low, the
AD7621 controls the acquisition phase and then automati-
cally initiates a new conversion. By keeping
CNVST
low,
the AD7621 keeps the conversion process running by itself.
It should be noted that the analog input has to be settled
when BUSY goes low. Also, at power-up,
CNVST
should be brought low once to initiate the conversion
process. In this mode, the AD7621 could sometimes run
slightly faster then the guaranteed limits in the impulse
mode. This feature does not exist in warp or normal modes.
t9
t8
RESET
DATA
BUS
BUSY
CNVST
Figure 13. RESET Timing
DIGITAL INTERFACE
The AD7621 has a versatile digital interface; it can be
interfaced with the host system by using either a serial or
parallel interface. The serial interface is multiplexed on
the parallel data bus. The AD7621 digital interface also
accommodates both 2.5V, 3.3V or 5V logic with either
OVDD at 2.5V or 3.3V. OVDD defines the logic high out-
put voltage. In most applications, the OVDD supply pin of
the AD7621 is connected to the host system interface 2.5V
or 3.3V digital supply. Finally, by using the OB/
2C
input
pin, both two’s complement or straight binary coding can
be used.
The two signals
CS
and
RD
control the interface. When
at least one of these signals is high, the interface outputs
are in high impedance. Usually,
CS
allows the selection of
each AD7621 in multi-circuits applications and is held
low in a single AD7621 design.
RD
is generally used to
enable the conversion result on the data bus.
t1
t3
t4
t11
CNVST
BUSY
DATA
BUS
CS = RD = 0
t10
PREVIOUS CONVERSION DATA
NEW DATA
Figure 14. Master Parallel Data Timing for Reading
(Continuous Read)
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