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參數(shù)資料
| 型號： | AD7641BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit 250/670 kSPS PulSAR Bipolar Programmable Inputs ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 192K |
| 代理商： | AD7641BCPZ |
AD7631/AD7634
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs/Outputs
IN+, IN, REF, REFBUFIN, TEMP,
INGND, REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
AVDD, DVDD
OVDD
AVDD to DVDD
AVDD, DVDD to OVDD
Digital Inputs
PDREF, PDBUF
Internal Power Dissipation
Internal Power Dissipation
Junction Temperature
Storage Temperature Range
1. Specification is for the device in free air:
48-Lead LQFP; θ
JA
= 91°C/W, θ
JC
= 30°C/W.
2. Specification is for the device in free air:
48-Lead LFCSP; θ
JA
= 26°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrC | Page 8 of 14
Rating
AVDD + 0.3 V to
AGND 0.3 V
±0.3 V
0.3 V to +2.7 V
0.3 V to +3.8 V
±2.8 V
3.8 V to +2.8 V
0.3 V to +5.5 V
±20 mA
700 mW
2.5 W
125°C
–65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
2
0
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, C = 10 pF
500
μ
A
I
OL
500
μ
A
I
OH
1.4V
TO OUTPUT
PIN
C
L
50pF
0.8V
t
DELAY
2V
2V
0.8V
0.8V
2V
t
DELAY
0
Figure 3. Voltage Reference Levels for Timing
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