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參數資料
| 型號： | AD7654 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| 中文描述： | 雙路2通道同步采樣SAR 500 kSPS的16位ADC |
| 文件頁數： | 16/24頁 |
| 文件大小： | 734K |
| 代理商： | AD7654 |
REV. 0
–16–
AD7654
t
1
t
3
t
4
t
17
CNVST
BUSY
DATA BUS
CS
=
RD
= 0
t
16
NEW A
OR B
EOC
PREVIOUS CHANNEL A
OR B
PREVIOUS CHANNEL B
OR NEW A
t
10
Figure 10. Master Parallel Data Timing for Read-
ing (Continuous Read)
DATA BUS
t
18
t
19
BUSY
CS
RD
CURRENT
CONVERSION
Figure 11. Slave Parallel Data Timing for Reading
(Read after Convert)
PREVIOUS
CONVERSION
t
1
t
3
t
18
t
19
t
4
CS
= 0
CNVST
,
RD
BUSY
DATA BUS
EOC
t
13
t
11
t
12
t
10
Figure 12. Slave Parallel Data Timing for Reading
(Read during Convert)
PARALLEL INTERFACE
The AD7654 is configured to use the parallel interface (Figure 10)
when the SER/
PAR
is held low. The data can be read either
after each conversion, which is during the next acquisition phase
or during the other channel’s conversion, or during the following
conversion as shown, respectively, in Figures 11 and 12. When the
data is read during the conversion, however, it is recommended
that it is read only during the first half of the conversion
phase. This avoids any potential feedthrough between voltage
transients on the digital interface and the most critical analog
conversion circuitry.
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 13, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped, the
LSB is output on D[15:8], and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
CS
RD
BYTE
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
HI-Z
HI-Z
t
18
t
18
t
19
Figure 13. 8-Bit Parallel Interface
CS
A/
B
RD
HI-Z
CHANNEL A
t
18
DATA BUS
t
20
CHANNEL B
HI-Z
Figure 14. A/
B
Channel Reading
The detailed functionality of A/
B
is explained in Figure 15.
When high, the data from channel A is available on the data bus.
When low, the data bus now carries output from channel B.
Note that channel A can be read immediately after conversion is
done (
EOC
), while channel B is still in its converting phase.
SERIAL INTERFACE
The AD7654 is configured to use the serial interface when the
SER/PAR is held high. The AD7654 outputs 32 bits of data,
MSB first, on the SDOUT pin. The order of the channels being
output is controlled by A/B. When high, channel A is output
first; when low, channel B is output first. Unlike in parallel
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| AD7654ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:16-BIT SIMULTANEOUS SAMPLING 500KSPS ADC - Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7654 LFSCP-48 |
| AD7654ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 500KSPS 16BIT PARALLEL/SERL 48LFCSP EP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:16-BIT SIMULTANEOUS SAMPLING 500KSPS ADC - Bulk |
| AD7654ACPZ | 功能描述:IC ADC 16BIT DUAL 2CH 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD7654ACPZRL | 功能描述:IC ADC 16BIT DUAL 2CH 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7654AST | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:16-BIT SIMULTANEOUS SAMPLING 500KSPS - Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7654 LQFP48 |
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