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參數資料
| 型號： | AD7654 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| 中文描述： | 雙路2通道同步采樣SAR 500 kSPS的16位ADC |
| 文件頁數： | 7/24頁 |
| 文件大小： | 734K |
| 代理商： | AD7654 |
REV. 0
AD7654
–7–
14
D[5]
DI/O
When SER/
PAR
is LOW, this output is used as Bit 5 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to select the
active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
When SER/
PAR
is LOW, this output is used as Bit 6 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to invert the
SCLK signal. It is active in both Master and Slave modes.
When SER/
PAR
is LOW, this output is used as Bit 7 of the Parallel Port Data Out-
put Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as either an exter-
nal data input or a read mode selection input, depending on the state of EXT/
INT
.
When EXT/
INT
is HIGH, RDC/SDIN can be used as a data input to daisy-chain the
conversion results from two or more ADCs onto a single SDOUT line. The digital
data level on SDIN is output on SDOUT with a delay of 32 SCLK periods after the
initiation of the read sequence.
When EXT/
INT
is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN
is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is
LOW, the data can be output on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply as the supply of
the host interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
When SER/
PAR
is LOW, this output is used as Bit 8 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a serial data
output synchronized to SCLK. Conversion results are stored in a 32-bit on-chip regis-
ter. The AD7654 provides the two conversion results, MSB first, from its internal shift
register. The order of channel outputs is controlled by A/B. In serial mode, when
EXT/
INT
is LOW, SDOUT is valid on both edges of SCLK.
In Serial Mode, when EXT/
INT
is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the
next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on
the next rising edge.
When SER/
PAR
is LOW, this output is used as Bit 9 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this pin, part of the serial port, is used as a serial data clock
input or output, dependent upon the logic state of the EXT/
INT
pin. The active edge
where the data SDOUT is updated depends on the logic state of the INVSCLK pin.
When SER/
PAR
is LOW, this output is used as Bit 10 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a digital output
frame synchronization for use with the internal data clock (EXT/
INT
= Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH
and frames SDOUT. After the first channel is output, SYNC is pulsed LOW. When
a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and
remains LOW while SDOUT output is valid. After the first channel is output, SYNC
is pulsed HIGH.
or INVSYNC
15
D[6]
DI/O
or INVSCLK
16
D[7]
DI/O
or RDC/SDIN
17
18
OGND
OVDD
P
P
19, 36
21
DVDD
D[8]
P
DO
or SDOUT
22
D[9]
DI/O
or SCLK
23
D[10]
DO
or SYNC
Pin No.
Mnemonic
Type
Description
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| AD7654ACPRL | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
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相關代理商/技術參數 |
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| AD7654ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:16-BIT SIMULTANEOUS SAMPLING 500KSPS ADC - Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7654 LFSCP-48 |
| AD7654ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 500KSPS 16BIT PARALLEL/SERL 48LFCSP EP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:16-BIT SIMULTANEOUS SAMPLING 500KSPS ADC - Bulk |
| AD7654ACPZ | 功能描述:IC ADC 16BIT DUAL 2CH 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD7654ACPZRL | 功能描述:IC ADC 16BIT DUAL 2CH 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7654AST | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:16-BIT SIMULTANEOUS SAMPLING 500KSPS - Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7654 LQFP48 |
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