- 您現在的位置：買賣IC網 > PDF目錄373913 > AD7677ASTRL (ANALOG DEVICES INC) 16-Bit, 1 LSB INL, 1 MSPS Differential ADC PDF資料下載
參數資料
| 型號： | AD7677ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 1 LSB INL, 1 MSPS Differential ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數： | 7/20頁 |
| 文件大小： | 322K |
| 代理商： | AD7677ASTRL |
REV. 0
AD7677
–7–
PIN FUNCTION DESCRIPTIONS (continued)
Pin
No.
Mnemonic
Type
Description
19
20
21
DVDD
DGND
DATA[8]
or SDOUT
P
P
DO
Digital Power. Nominally at 5 V.
Digital Power Ground
When SER/
PAR
is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7677
provides the conversion result, MSB first, from its internal shift register. The DATA format is
determined by the logic level of OB/
2C
. In serial mode, when EXT/
INT
is LOW, SDOUT
is valid on both edges of SCLK. In serial mode, when EXT/
INT
is HIGH: If INVSCLK is
LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK
is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
When SER/
PAR
is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT
pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/
PAR
is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT
= Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
When SER/
PAR
is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH and EXT/
INT
is HIGH, this output, part of the serial port, is used
as an incomplete read error flag. In slave mode, when a data read is started and not complete
when the following conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard-
less of the state of SER/
PAR
.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
Must be tied to digital ground.
Read Data. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
CS
is also used to gate the external serial clock.
Reset Input. When set to a logic HIGH, reset the AD7677. Current conversion if any is aborted.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
Start Conversion. A falling edge on
CNVST
puts the internal sample/hold into the hold state and
initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if
CNVST
is
held low when the acquisition phase
(
t
8
) is complete, the internal sample/hold is put into the
hold state and a conversion is immediately started.
Must be Tied to Analog Ground.
Reference Input Voltage
Reference Input Analog Ground
Differential Negative Analog Input
Differential Positive Analog Input
22
DATA[9]
or SCLK
DI/O
23
DATA[10]
or SYNC
DO
24
DATA[11]
or RDERROR
DO
25–28
DATA[12:15]
DO
29
BUSY
DO
30
31
32
DGND
RD
CS
P
DI
DI
33
34
RESET
PD
DI
DI
35
CNVST
DI
36
37
38
39
43
AGND
REF
REFGND
IN–
IN+
P
AI
AI
AI
AI
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
相關PDF資料 |
PDF描述 |
|---|---|
| AD7679CB1 | 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC |
| AD7694 | 16-Bit, 250 kSPS PulSAR ADC in MSOP |
| AD7694ARM | 16-Bit, 250 kSPS PulSAR ADC in MSOP |
| AD7694ARMRL7 | 16-Bit, 250 kSPS PulSAR ADC in MSOP |
| AD7694BRM | 16-Bit, 250 kSPS PulSAR ADC in MSOP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7677ASTZ | 功能描述:IC ADC 16BIT 1MSPS DIFF 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7677ASTZ | 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
| AD7677ASTZRL | 功能描述:IC ADC 16BIT 1MSPS DIFF 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD7678 | 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC |
| AD7678ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 18-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:18-BIT,100KSPSSARADC - Bulk 制造商:Analog Devices 功能描述:18BIT SAR ADC SMD 7678 LFSCP-48 |
發布緊急采購，3分鐘左右您將得到回復。