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參數(shù)資料
| 型號： | AD7701AQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 16-Bit A/D Converter |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 312K |
| 代理商： | AD7701AQ |
–13–
REV. D
AD7701
AGND
AD7701
DGND
AV
DD
V
REF
10k
10k
0.1
μ
F
0.1
μ
F
DV
DD
AV
SS
DV
SS
0.1
μ
F
REF
10V
±
1V
AD707
0.1
μ
F
Figure 17. Single Supply Operation
SLE E P MODE
T he low power standby mode is initiated by taking the
SLEEP
input low, which shuts down all analog and digital circuits and
reduces power consumption to 10
μ
W. T he calibration coeffi-
cients are still retained in memory, but as the converter has been
quiescent, it is necessary to wait for the filter settling time
(507,904 cycles) before accessing the output data.
DIGIT AL INT E RFACE
T he AD7701’s serial communications port allows easy inter-
facing to industry-standard microprocessors. T hree different
modes of operations are available, optimized for different types
of interface.
SY NCHRONOUS SE LF-CLOCK ING MODE (SSC)
T he SSC mode (MODE pin high) allows easy interfacing to
serial-parallel conversion circuits in systems with parallel data
communication. T his mode allows interfacing to 74X X 299
Universal Shift registers without any additional decoding. T he
SSC mode can also be used with microprocessors such as the
68HC11 and 68HC05, which allow an external device to clock
their serial port.
Figure 18 shows the timing diagram for the SSC mode. Data is
clocked out by an internally generated serial clock. T he AD7701
divides each sampling interval into sixteen distinct periods.
Eight periods of 64 clock pulses are for analog settling and eight
periods of 64 clock pulses are for digital computation. T he
status of
CS
is polled at the beginning of each digital computation
period. If it is low at any of these times then SCLK will become
active and the data word currently in the output register will be
transmitted, MSB first. After the LSB has been transmitted
DRDY
goes high and SDAT A goes three-state. If
CS
, having
been brought low, is taken high again at any time during data
transmission, SDAT A and SCLK will go three-state after the
current bit finishes. If
CS
is subsequently brought low,
transmission will resume with the next bit during the sub-
sequent digital computation period. If transmission has not been
initiated and completed by the time the next data word is
available,
DRDY
will go high for four clock cycles then low
again as the new word is loaded into the output register.
A more detailed diagram of the data transmission in the SSC
mode is shown in Figure 19. Data bits change on the falling
edge of SCLK and are valid on the rising edge of SCLK .
ANALOG SETTLING
DIGITAL COMPUTATION
SCLK (O)
SDATA (O)
HI-Z
HI-Z
HI-Z
HI-Z
MSB
LSB
DRDY (O)
DIGITAL COMPUTATION
CS POLLED
CS (I)
INTERNAL
STATUS
72 CLKIN CYCLES
64 CLKIN CYCLES
64 CLKIN CYCLES
1024 CLKIN CYCLES
Figure 18. Timing Diagram for SSC Data Transmission Mode
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| AD7701AR | 功能描述:IC ADC 16BIT LC2MOS 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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| AD7701ARS-REEL | 功能描述:IC ADC 16BIT LC2MOS MONO 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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