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參數(shù)資料
| 型號： | AD7703SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 20-Bit A/D Converter |
| 中文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 251K |
| 代理商： | AD7703SQ |
AD7703
–14–
REV. D
SY NCHRONOUS SE LF-CLOCK ING MODE (SSC)
T he SSC mode (MODE pin high) allows easy interfacing to
serial-parallel conversion circuits in systems with parallel data
communication. T his mode allows interfacing to 74X X 299
Universal Shift registers without any additional decoding. T he
SSC mode can also be used with microprocessors such as the
68HC11 and 68HC05, which allow an external device to clock
their serial port.
Figure 15 shows the timing diagram for the SSC mode. Data is
clocked out by an internally generated serial clock. T he
AD7703 divides each sampling interval into sixteen distinct
periods. Eight periods of 64 clock pulses are for analog settling
and eight periods of 64 clock pulses are for digital computation.
T he status of
CS
is polled at the beginning of each digital
computation period. If it is low at any of these times, then
SCLK will become active and the data word currently in the
output register will be transmitted, MSB first. After the LSB has
been transmitted
DRDY
will go high until the new data word
becomes available. If
CS
, having been brought low, is taken
high again at any time during data transmission, SDAT A and
SCLK will go three-state after the current bit finishes. If
CS
is
subsequently brought low, transmission will resume with the
next bit during the subsequent digital computation period. If
transmission has not been initiated and completed by the time
the next data word is available,
DRDY
will go high for four
clock cycles then low again as the new word is loaded into the
output register.
A more detailed diagram of the data transmission in the SSC
mode is shown in Figure 16. Data bits change on the falling
edge of SCLK and are valid on the rising edge of SCLK .
ANALOG TIME 0
DIGITAL TIME 7
SCLK (O)
SDATA (O)
HI-Z
HI-Z
HI-Z
HI-Z
MSB
DRDY (O)
DIGITAL TIME 0
CS POLLED
CS (I)
INTERNAL
STATUS
72 CLKIN CYCLES
64 CLKIN
CYCLES
64 CLKIN
CYCLES
1024 CLKIN CYCLES
LSB
Figure 15. Timing Diagram for SSC Data Transmission Mode
CLKIN (I)
DRDY (O)
SDATA (O)
DB19 (MSB)
DB18
DB2
DB1
DB0 (LSB)
HI-Z
HI-Z
SCLK (O)
HI-Z
HI-Z
CS (I)
72
CLKIN
CYCLES
DB17
Figure 16. SSC Mode Showing Data Timing Relative to SCLK
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