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參數資料
| 型號： | AD7703SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 20-Bit A/D Converter |
| 中文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 251K |
| 代理商： | AD7703SQ |
AD7703
REV. D
–7–
T HE ORY OF OPE RAT ION
T he general block diagram of a sigma-delta ADC is shown in
Figure 8. It contains the following elements:
1. A sample-hold amplifier
2. A differential amplifier or subtracter
3. An analog low-pass filter
4. A 1-bit A/D converter (comparator)
5. A 1-bit DAC
6. A digital low-pass filter
ANALOG
LOW-PASS
FILTER
COMPARATOR
DIGITAL
FILTER
DIGITAL DATA
S/H AMP
DAC
Figure 8. General Sigma-Delta ADC
In operation, the sampled analog signal is fed to the subtracter,
along with the output of the 1-bit DAC. T he filtered difference
signal is fed to the comparator, whose output samples the
difference signal at a frequency many times that of the analog
signal frequency (oversampling).
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
SNR
=
(6.02
×
number of bits
+
1.76)
dB
,
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
T he AD7703 samples the input signal at 16 kHz, which spreads
the quantization noise from 0 kHz to 8 kHz. Since the specified
analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz,
the noise energy in this bandwidth would be only 1/800 of the
total quantization noise, assuming that the noise energy was
spread evenly throughout the spectrum. It is reduced still
further by analog filtering in the modulator loop, which shapes
the quantization noise spectrum to move most of the noise
energy to frequencies above 10 Hz. T he SNR performance in
the 0 Hz to 10 Hz range is conditioned to the 20-bit level in this
fashion.
T he output of the comparator provides the digital input for the
1-bit DAC, so the system functions as a negative feedback loop
which minimizes the difference signal. T he digital data that
represents the analog input voltage is in the duty cycle of the
pulse train appearing at the output of the comparator. It can be
retrieved as a parallel binary data word using a digital filter.
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma-
delta ADC is shown in Figure 8. T his contains only a first-order
low-pass filter or integrator.
T he AD7703 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled
output. After power-up or if there is a step change in the input
voltage, there is a settling time before valid data is obtained.
GE NE RAL DE SCRIPT ION
T he AD7703 is a 20-bit A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those representing chemical,
physical or biological processes. It contains a charge-balancing
(sigma-delta) ADC, calibration microcontroller with on-chip
static RAM, a clock oscillator and a serial communications port.
T he analog input signal to the AD7703 is continuously sampled
at a rate determined by the frequency of the master clock,
CLK IN. A charge-balancing A/D converter (sigma-delta modu-
lator) converts the sampled signal into a digital pulse train
whose duty cycle contains the digital information. A six-pole
Gaussian digital low-pass filter processes the output of the
sigma-delta modulator and updates the 20-bit output register at
a 4 kHz rate. T he output data can be read from the serial port
randomly or periodically at any rate up to 4 kHz.
AD7703
MODE
SDATA
SC1
SC2
DGND
CLKOUT
CLKIN
AGND
SCLK
CAL
CS
BP/UP
DV
SS
DV
DD
SLEEP
RANGE
CALIBRATE
AINPUT
ANALOG
SUPPLY
0.1
μ
F
SERIAL
SERIAL
READ
DATA
SUPPLY
2.5V
0.1
μ
F
0.1
μ
F
DRDY
0.1
μ
F
10
μ
F
AV
DD
V
REF
A
IN
AV
SS
VOLTAGE
REFERENCE
10
μ
F
Figure 7. Typical System Connection Diagram
T he AD7703 can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. A calibration cycle may be initiated at any time
using the CAL control input.
Other system components may also be included in the
calibration loop to remove offset and gain errors in the input
channel.
For battery operation, the AD7703 also offers a standby mode
that reduces idle power consumption to typically 10
μ
W.
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