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參數資料
型號: AD7703SQ
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: LC2MOS 20-Bit A/D Converter
中文描述: 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP20
封裝: CERDIP-20
文件頁數: 6/16頁
文件大小: 251K
代理商: AD7703SQ
AD7703
–6–
REV. D
PIN FUNCT ION DE SCRIPT ION
Pin
Mnemonic
Description
1
MODE
Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC)
mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB com-
ing first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode.
SCLK is configured as an output, with a clock frequency for f
CLK IN
/4 and 25% duty cycle.
Clock Output to generate an Internal Master Clock by connecting a crystal between CLK OUT and CLK IN.
If an external clock is used, CLK OUT is not connected.
Clock Input for External Clock.
System Calibration Pins. T he state of these pins, when CAL is taken high, determines the type of calibration
performed.
Digital Ground. Ground reference for all digital signals.
Digital Negative Supply, –5 V nominal.
Analog Negative Supply, –5 V nominal.
Analog Ground. Ground reference for all analog signals.
Analog Input.
Voltage Reference Input, +2.5 V nominal. T his determines the value of positive full-scale in the unipolar
mode and of both positive and negative full-scale in the Bipolar Mode.
Sleep mode pin. When this pin is taken low, the AD7703 goes into a low-power mode with typically 10
μ
W
power consumption.
Bipolar/Unipolar mode pin. When this pin is Low, the AD7703 is configured for a unipolar input range going
from AGND to V
REF
. When Pin 12 is High, the AD7703 is configured for a bipolar input range,
±
V
REF
.
Calibration mode pin. When CAL is taken High for more than 4 cycles, the AD7703 is reset and performs a
calibration cycle when CAL is brought Low again. T he CAL pin can also be used as a strobe to synchronize
the operation of several AD7703s.
Analog Positive Supply, +5 V nominal.
Digital Positive Supply, +5 V nominal.
Chip Select Input. When
CS
is brought low, the AD7703 will begin to transmit serial data in a format deter-
mined by the state of the MODE pin.
Data Ready Output.
DRDY
is low when valid data is available in the output register. It goes high after trans-
mission of a word is completed. It also goes high for four clock cycles when a new data word is being loaded
into the output register, to indicate that valid data is not available, irrespective of whether data transmission is
complete or not.
Serial Clock Input/Output. T he SCLK pin in configured as an input or output, dependent on the type of se-
rial data transmission that has been selected by the MODE pin. When configured as an output in the Syn-
chronous Self-Clocking mode, it has a frequency of f
CLK IN
/4 and a duty cycle of 25%.
Serial Data Output. T he AD7703’s output data is available at this pin as a 20-bit serial word.
2
CLK OUT
3
4, 17
CLK IN
SC1, SC2
5
6
7
8
9
10
DGND
DV
SS
AV
SS
AGND
A
IN
V
REF
11
SLEEP
12
BP/
UP
13
CAL
14
15
16
AV
DD
DV
DD
CS
18
DRDY
19
SCLK
20
SDAT A
T able I. Bit Weight T able (2.5 V Reference Voltage)
UNIPOLAR MODE
LSBs
% FS
BIPOLAR MODE
ppm FS LSBs
m
V
% FS
ppm FS
0.596
1.192
2.384
4.768
9.537
0.25
0.5
1.00
2.00
4.00
0.0000238
0.0000477
0.0000954
0.0001907
0.0003814
0.24
0.48
0.95
1.91
3.81
0.13
0.26
0.5
1.00
2.00
0.0000119
0.0000238
0.0000477
0.0000954
0.0001907
0.12
0.24
0.48
0.95
1.91
PIN CONFIGURAT ION
DIP, Cerdip, SOIC
MODE
SC1
DGND
DV
SS
AV
SS
CLKOUT
CLKIN
AGND
A
IN
V
REF
SDATA
SCLK
SC2
CAL
AV
DD
DV
DD
DRDY
CS
BP/UP
SLEEP
TOP VIEW
(Not to Scale)
AD7703
1
2
3
4
5
6
7
8
9
10
14
13
12
11
20
19
18
17
16
15
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