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| 型號： | AD7706* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V/5 V. 1 mW 2-/3-Channel 16-Bit. Sigma-Delta ADCs |
| 中文描述： | 3 V / 5號五，1毫瓦2-/3-Channel 16位。 Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大小： | 264K |
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AD7705/AD7706
–8–
REV. A
Table II. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V
Filter First
Notch and O/P
Data Rate
Typical Peak-to-Peak Resolution Bits
Gain of
Gain of
4
8
–3dB
Frequency
Gain of
1
Gain of
2
Gain of
16
Gain of
32
Gain of
64
Gain of
128
MCLK IN = 2.4576 MHz
50Hz
60Hz
250Hz
500Hz
MCLK IN = 1 MHz
20Hz
25Hz
100Hz
200Hz
13.1Hz
15.72Hz
65.5Hz
131Hz
16
16
13
10
16
16
13
10
16
16
13
10
16
16
13
10
16
15
13
10
16
14
13
10
15
14
12
10
14
13
12
10
5.24Hz
6.55Hz
26.2Hz
52.4Hz
16
16
13
10
16
16
13
10
16
16
13
10
16
16
13
10
16
15
13
10
16
14
13
10
15
14
12
10
14
13
12
10
OUTPUT NOISE (3 V OPERATION)
Table III shows the AD7705/AD7706 output rms noise for the selectable notch and –3dB frequencies for the part, as selected by
FS0 and FS1 of the Clock Register. The numbers given are for the bipolar input ranges with a V
REF
of +1.225V and a V
DD
= 3 V.
These numbers are typical and are generated at an analog input voltage of 0V with the part used in either buffered or unbuffered
mode. Table II meanwhile shows the output
peak-to-peak
noise for the selectable notch and –3 dB frequencies for the part.
It is im-
portant to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but
on peak-to-peak noise.
The numbers given are for bipolar input ranges with a V
REF
of +1.225 V and for either buffered or unbuffered
mode. These numbers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Regis-
ter set to 0.
Table III. Output RMS Noise vs. Gain and Output Update Rate @ 3 V
Filter First
Notch and O/P
Data Rate
Typical Output RMS Noise in
m
V
Gain of
Gain of
4
8
–3dB
Frequency
Gain of
1
Gain of
2
Gain of
16
Gain of
32
Gain of
64
Gain of
128
MCLK IN = 2.4576 MHz
50Hz
60Hz
250Hz
500Hz
MCLK IN = 1 MHz
20Hz
25Hz
100Hz
200Hz
13.1Hz
15.72Hz
65.5Hz
131Hz
3.8
5.1
50
270
2.4
2.9
25
135
1.5
1.7
14
65
1.3
1.5
9.9
41
1.1
1.2
5.1
22
1.0
1.0
2.6
9.7
0.9
0.9
2.3
5.1
0.9
0.9
2.0
3.3
5.24Hz
6.55Hz
26.2Hz
52.4Hz
3.8
5.1
50
270
2.4
2.9
25
135
1.5
1.7
14
65
1.3
1.5
9.9
41
1.1
1.2
5.1
22
1.0
1.0
2.6
9.7
0.9
0.9
2.3
5.1
0.9
0.9
2.0
3.3
Table IV. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V
Fi
lter First
Notch and O/P
Data Rate
M
CLK IN = 2.4576 MHz
50Hz
60Hz
250Hz
500Hz
MCLK IN = 1 MHz
20Hz
25Hz
100Hz
200Hz
Typical Peak-to-Peak Resolution in Bits
Gain of
Gain of
Gain of
2
4
8
–3dB
Frequency
Gain of
1
Gain of
16
Gain of
32
Gain of
64
Gain of
128
13.1Hz
15.72Hz
65.5Hz
131Hz
16
16
13
10
16
16
13
10
15
15
13
10
15
14
13
10
14
14
12
10
13
13
12
10
13
13
11
10
12
12
11
10
5.24Hz
6.55Hz
26.2Hz
52.4Hz
16
16
13
10
16
16
13
10
15
15
13
10
15
14
13
10
14
14
12
10
13
13
12
10
13
13
11
10
12
12
11
10
相關(guān)PDF資料 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7706BN | 功能描述:IC ADC 16BIT 3CH 16-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7706BNZ | 功能描述:IC ADC 16BIT 3CHAN 16DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7706BNZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs |
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