- 您現在的位置：買賣IC網 > PDF目錄373913 > AD7706BR (ANALOG DEVICES INC) 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs PDF資料下載
參數資料
| 型號： | AD7706BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| 中文描述： | 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.300 INCH, MS-013AA, SOIC-16 |
| 文件頁數： | 12/32頁 |
| 文件大小： | 264K |
| 代理商： | AD7706BR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD7705/AD7706
–12–
REV. A
Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 01Hex
The Setup Register is an eight bit register from which data can either be read or to which data can be written. Table IX outlines the
bit designations for the Setup Register.
Table IX. Setup Register
MD1 (0)
MD0 (0)
G2 (0)
G1 (0)
G0 (0)
B
/U (0)
BUF (0)
FSYNC (1)
MD1
MD0
Operating Mode
0
0
Normal Mode: this is the normal mode of operation of the device whereby the device is performing normal
conversions.
Self-Calibration: this activates self-calibration on the channel selected by CH1 and CH0 of the Communica-
tions Register. This is a one-step calibration sequence and when complete the part returns to Normal Mode
with MD1 and MD0 returning to 0, 0. The
DRDY
output or bit goes high when calibration is initiated and
returns low when this self-calibration is complete and a new valid word is available in the data register. The
zero-scale calibration is performed at the selected gain on internally shorted (zeroed) inputs and the full-
scale calibration is performed at the selected gain on an internally-generated V
REF
/Selected Gain.
Zero-Scale System Calibration: this activates zero scale system calibration on the channel selected by CH1
and CH0 of the Communications Register. Calibration is performed at the selected gain on the input volt-
age provided at the analog input during this calibration sequence. This input voltage should remain stable
for the duration of the calibration. The
DRDY
output or bit goes high when calibration is initiated and
returns low when this zero-scale calibration is complete and a new valid word is available in the data register.
At the end of the calibration, the part returns to Normal Mode with MD1 and MD0 returning to 0, 0.
Full-Scale System Calibration: this activates full-scale system calibration on the selected input channel.
Calibration is performed at the selected gain on the input voltage provided at the analog input during this
calibration sequence. This input voltage should remain stable for the duration of the calibration. Once
again, the
DRDY
output or bit goes high when calibration is initiated and returns low when this full-scale
calibration is complete and a new valid word is available in the data register. At the end of the calibration,
the part returns to Normal Mode with MD1 and MD0 returning to 0, 0.
0
1
1
0
1
1
G2–G0
Gain Selection Bits. These bits select the gain setting for the on-chip PGA as outlined in Table X.
Table X. Gain Selection
G2
G1
G0
Gain Setting
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
B
/U
BUF
Bipolar/Unipolar Operation. A “0” in this bit selects Bipolar Operation. A “1” in this bit selects Unipolar Operation.
Buffer Control. With this bit at “0,” the on-chip buffer on the analog input is shorted out. With the buffer shorted
out, the current flowing in the V
DD
line is reduced. When this bit is high, the on-chip buffer is in series with the
analog input allowing the input to handle higher source impedances.
Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the calibra-
tion control logic are held in a reset state and the analog modulator is also held in its reset state. When this bit
goes low, the modulator and filter start to process data and a valid word is available in 3
×
1/(output update rate),
i.e., the settling time of the filter. This FSYNC bit does not affect the digital interface and does not reset the
DRDY
output if it is low.
FSYNC
相關PDF資料 |
PDF描述 |
|---|---|
| AD7706BRU | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| AD7705EB | Precision Zero-Drift Operational Amplifier with Internal Capacitors; Package: SO; No of Pins: 8; Temperature Range: 0°C to +70°C |
| AD7706* | 3 V/5 V. 1 mW 2-/3-Channel 16-Bit. Sigma-Delta ADCs |
| AD7706EB | High Performance Switched Capacitor Universal Filter; Package: PDIP; No of Pins: 14; Temperature Range: 0°C to +70°C |
| AD7706(中文) | 3 V/5 V, 1 Mw 2-/3-Channel 16-Bit, Sigma-Delta ADCs(三輸入通道16位A/D轉換器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7706BR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 16-Pin SOIC W T/R |
| AD7706BR-REEL7 | 功能描述:IC ADC 16BIT 3CH 16-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:16 采樣率（每秒）:45k 數據接口:串行 轉換器數目:2 功率耗散（最大）:315mW 電壓電源:模擬和數字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數目和類型:2 個單端，單極 |
| AD7706BRU | 功能描述:IC ADC 16BIT 3CH 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7706BRU-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 16TSSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:LOW COST 3CHNL 16-6 SIGMA DELTA ADC I.C. - Tape and Reel |
| AD7706BRU-REEL7 | 功能描述:IC ADC 16BIT 3CH 16-TSSOP T/R RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:16 采樣率（每秒）:45k 數據接口:串行 轉換器數目:2 功率耗散（最大）:315mW 電壓電源:模擬和數字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數目和類型:2 個單端，單極 |
發布緊急采購，3分鐘左右您將得到回復。