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參數資料
| 型號： | AD7706BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| 中文描述： | 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.300 INCH, MS-013AA, SOIC-16 |
| 文件頁數： | 7/32頁 |
| 文件大小： | 264K |
| 代理商： | AD7706BR |
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AD7705/AD7706
–7–
REV. A
Pin No.
Mnemonic
Function
10
REF IN(–)
Reference Input. Negative input of the differential reference input to the AD7705/AD7706.
The REFIN(–) can lie anywhere between V
DD
and GND provided REFIN(+) is greater
than REFIN(–).
AD7705: Negative input of the differential analog Input Channel 2. AD7706: Analog Input
Channel 3.
Logic Output. A logic low on this output indicates that a new output word is available from
the AD7705/AD7706 data register. The
DRDY
pin will return high upon completion of a
read operation of a full output word. If no data read has taken place between output updates,
the
DRDY
line will return high for 500
×
t
CLKIN
cycles prior to the next output update.
While
DRDY
is high, a read operation should neither be attempted nor in progress to avoid
reading from the data register as it is being updated. The
DRDY
line will return low again
when the update has taken place.
DRDY
is also used to indicate when the AD7705/AD7706
has completed its on-chip calibration sequence.
Serial Data Output with serial data being read from the output shift register on the part. This
output shift register can contain information from the setup register, communications regis-
ter, clock register or data register, depending on the register selection bits of the Communica-
tions Register.
Serial Data Input with serial data being written to the input shift register on the part. Data
from this input shift register is transferred to the setup register, clock register or communica-
tions register, depending, on the register selection bits of the Communications Register.
Supply Voltage, +2.7 V to +5.25 V operation.
Ground reference point for the AD7705/AD7706’s internal circuitry.
11
AIN2(–)[AIN3]
12
DRDY
13
DOUT
14
DIN
15
16
V
DD
GND
OUTPUT NOISE (5 V OPERATION)
Table I shows the AD7705/AD7706 output rms noise for the selectable notch and –3dB frequencies for the part, as selected by FS0
and FS1 of the Clock Register. The numbers given are for the bipolar input ranges with a V
REF
of +2.5V and V
DD
= 5 V. These
numbers are typical and are generated at an analog input voltage of 0V with the part used in either buffered or unbuffered mode. Table II
meanwhile shows the output
peak-to-peak
noise for the selectable notch and –3 dB frequencies for the part.
It is important to note that
these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak
noise.
The numbers given are for bipolar input ranges with a V
REF
of +2.5 V and for either buffered or unbuffered mode. These num-
bers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Register set to 0.
Table I. Output RMS Noise vs. Gain and Output Update Rate @ 5 V
Filter First
Notch and O/P
Data Rate
Typical Output RMS Noise in
m
V
Gain of
Gain of
4
8
–3dB
Frequency
Gain of
1
Gain of
2
Gain of
16
Gain of
32
Gain of
64
Gain of
128
MCLK IN = 2.4576 MHz
50Hz
60Hz
250Hz
500Hz
MCLK IN = 1 MHz
20Hz
25Hz
100Hz
200Hz
13.1Hz
15.72Hz
65.5Hz
131Hz
4.1
5.1
110
550
2.1
2.5
49
285
1.2
1.4
31
145
0.75
0.8
17
70
0.7
0.75
8
41
0.66
0.7
3.6
22
0.63
0.67
2.3
9.1
0.6
0.62
1.7
4.7
5.24Hz
6.55Hz
26.2Hz
52.4Hz
4.1
5.1
110
550
2.1
2.5
49
285
1.2
1.4
31
145
0.75
0.8
17
70
0.7
0.75
8
41
0.66
0.7
3.6
22
0.63
0.67
2.3
9.1
0.6
0.62
1.7
4.7
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