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參數資料
| 型號： | AD7712EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC 2 MOS Signal Conditioning ADC(229.08 k) |
| 中文描述： | 立法會二馬鞍山信號調理模數轉換器（229.08十一） |
| 文件頁數： | 15/28頁 |
| 文件大小： | 229K |
| 代理商： | AD7712EB |
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2
–15–
REV. E
AD7712
Table IV. Typical External Series Resistance That Will Not
Introduce 16-Bit Gain Error
External Capacitance (pF)
50
100
45.3 k
27.1 k
7.3 k
88.6 k
22.1 k
13.2 k
3.6 k
41.4 k
10.6 k
6.3 k
17.6 k
4.8 k
Gain
0
184 k
500
1000
4.1 k
2.0 k
970
440
5000
1.1 k
560
270
120
1
2
4
8–128
1.7 k
790
2.9 k
Table V. Typical External Series Resistance That Will Not
Introduce 20-Bit Gain Error
External Capacitance (pF)
50
100
34.5 k
20.4 k
5.2 k
70.5 k
16.9 k
10 k
31.8 k
8.0 k
13.4 k
3.6 k
Gain
0
145 k
500
1000
2.8 k
1.4 k
670
300
5000
700
350
170
80
1
2
4
8–128
2.5 k
1.2 k
550
4.8 k
2.2 k
The numbers in the above tables assume a full-scale change on
the analog input. In any case, the error introduced due to longer
charging times is a gain error which can be removed using the
system calibration capabilities of the AD7712 provided that the
resultant span is within the span limits of the system calibration
techniques for the AD7712.
The AIN2 input contains a resistive attenuation network as
outlined in Figure 8. The typical input impedance on this input
is 44 k
. As a result, the AIN2 input should be driven from a
low impedance source.
33k
V
V
BIAS
AIN2
11k
V
MODULATOR
CIRCUIT
Figure 8. AIN2 Input Impedance
Antialias Considerations
The digital filter does not provide any rejection at integer mul-
tiples of the modulator sample frequency (n
×
19.5 kHz, where
n = 1, 2, 3 . . . ). This means that there are frequency bands,
±
f
3 dB
wide (f
3 dB
is cutoff frequency selected by FS0 to FS11)
where noise passes unattenuated to the output. However, due to
the AD7712’s high oversampling ratio, these bands occupy only
a small fraction of the spectrum and most broadband noise is
filtered. In any case, because of the high oversampling ratio a
simple, RC, single pole filter is generally sufficient to attenuate
the signals in these bands on the analog input and thus provide
adequate antialiasing filtering.
If passive components are placed in front of the AIN1 input of
the AD7712, care must be taken to ensure that the source imped-
ance is low enough so as not to introduce gain errors in the sys-
tem. The dc input impedance for the AIN1 input is over 1 G
.
The input appears as a dynamic load that varies with the clock
frequency and with the selected gain (see Figure 7). The input
sample rate, as shown in Table III, determines the time allowed
for the analog input capacitor, C
IN
, to be charged. External
impedances result in a longer charge time for this capacitor, and
this may result in gain errors being introduced on the analog
inputs. Table IV shows the allowable external resistance/
capacitance values such that no gain error to the 16-bit level
is introduced while Table V shows the allowable external
resistance/capacitance values such that no gain error to the
20-bit level is introduced. Both inputs of the differential input
channels (AIN1) look into similar input circuitry.
R
INT
(7k
V
TYP)
C
INT
(11.5pF TYP)
V
BIAS
AIN
SWITCHING FREQUENCY DEPENDS ON
f
CLKIN
AND SELECTED GAIN
HIGH
IMPEDANCE
>1G
V
Figure 7. AIN1 Input Impedance
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