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參數資料
| 型號： | AD7712EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC 2 MOS Signal Conditioning ADC(229.08 k) |
| 中文描述： | 立法會二馬鞍山信號調理模數轉換器（229.08十一） |
| 文件頁數： | 7/28頁 |
| 文件大小： | 229K |
| 代理商： | AD7712EB |
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2
–7–
REV. E
AD7712
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
1
SCLK
Serial Clock. Logic Input/Output depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode and the SCLK pin provides a serial clock output. This SCLK becomes
active when
RFS
or
TFS
goes low and it goes high impedance when either
RFS
or
TFS
returns high or when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7712 in smaller batches of data.
Master Clock signal for the device. This can be provided in the form of a crystal or external clock. A crystal can
be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.
When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
Address Input. With this input low, reading and writing to the device is to the control register. With this input
high, access is to either the data register or the calibration registers.
Logic Input which allows for synchronization of the digital filters when using a number of AD7712s. It resets
the nodes of the digital filter.
Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its
external clocking mode.
Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input
is connected to an output current source which can be used to check that an external transducer has burned out
or gone open circuit. This output current source can be turned on/off via the control register.
Analog Input Channel 1. Negative input of the programmable gain differential analog input.
Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power
consumption to less than 50
μ
W.
Test Pin. Used when testing the device. Do not connect anything to this pin.
Analog Negative Supply, 0 V to –5 V. Tied to AGND for single supply operation. The input voltage on AIN1
should not go > 30 mV negative w.r.t. V
SS
for correct operation of the device.
Analog Positive Supply Voltage, +5 V to +10 V.
Input Bias Voltage. This input voltage should be set such that V
BIAS
+ 0.85
×
V
REF
< AV
DD
and V
BIAS
– 0.85
×
V
REF
> V
SS
where V
REF
is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AV
DD
and V
SS
. Thus, with AV
DD
= +5 V and V
SS
= 0 V, it can be tied to REF OUT; with AV
DD
= +5 V and V
SS
=
–5 V, it can be tied to AGND, while with AV
DD
= +10 V, it can be tied to +5 V.
Reference Input. The REF IN(–) can lie anywhere between AV
DD
and V
SS
provided REF IN(+) is greater
than REF IN(–).
Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).
REF IN(+) can lie anywhere between AV
DD
and V
SS
.
Reference Output. The internal +2.5 V reference is provided at this pin. This is a single-ended output
which is referred to AGND.
Analog Input Channel 2. High level analog input which accepts an analog input voltage range of
±
4
×
V
REF
/GAIN. At the nominal V
REF
of +2.5 V and a gain of 1, the AIN2 input voltage range is
±
10 V.
Ground reference point for analog circuitry.
Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial
data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active
after
TFS
goes low. In the external clocking mode,
TFS
must go low before the first bit of the data word
is written to the part.
Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the
self-clocking mode, the SCLK and SDATA lines both become active after
RFS
goes low. In the external
clocking mode, the SDATA line becomes active after
RFS
goes low.
2
MCLK IN
3
4
MCLK OUT
A0
5
SYNC
6
MODE
7
AIN1(+)
8
9
AIN1(–)
STANDBY
10
11
TP
V
SS
12
13
AV
DD
V
BIAS
14
REF IN(–)
15
REF IN(+)
16
REF OUT
17
AIN2
18
19
AGND
TFS
20
RFS
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