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參數資料
| 型號： | AD7712SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Signal Conditioning ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數： | 23/28頁 |
| 文件大小： | 229K |
| 代理商： | AD7712SQ |
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2
–23–
REV. E
AD7712
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the
DRDY
line, and the write operation does not have any effect
on the status of
DRDY
. A write operation to the control regis-
ter or the calibration register must always write 24 bits to the
respective register.
Figure 14a shows a write operation to the AD7712 with
TFS
remaining low for the duration of the write operation. A0 deter-
mines whether a write operation transfers data to the control
register or to the calibration registers. This A0 signal must
remain valid for the duration of the serial write operation. As
before, the serial clock line should be low between read and
write operations. The serial data to be loaded to the AD7712
must be valid on the high level of the externally applied SCLK
signal. Data is clocked into the AD7712 on the high level of this
SCLK signal with the MSB transferred first. On the last active
high time of SCLK, the LSB is loaded to the AD7712.
Figure 14b shows a timing diagram for a write operation to the
AD7712 with
TFS
returning high during the write operation
and returning low again to write the rest of the data word. Tim-
ing parameters and functions are very similar to that outlined for
Figure 14a, but Figure 14b has a number of additional times to
show timing relationships when
TFS
returns high in the middle
of transferring a word.
Data to be loaded to the AD7712 must be valid prior to the
rising edge of the SCLK signal.
TFS
should return high during
the low time of SCLK. After
TFS
returns low again, the next bit
of the data word to be loaded to the AD7712 is clocked in on
next high level of the SCLK input. On the last active high time
of the SCLK input, the LSB is loaded to the AD7712.
SCLK (I)
SDATA (I)
TFS
(I)
A0 (I)
MSB
LSB
t
32
t
33
t
26
t
27
t
35
t
36
t
34
Figure 14a. External Clocking Mode, Control/Calibration Register Write Operation
SCLK (I)
SDATA (I)
TFS
(I)
A0 (I)
MSB
BIT N
BIT N+1
t
32
t
26
t
30
t
35
t
27
t
36
t
35
t
36
Figure 14b. External Clocking Mode, Control/Calibration Register Write Operation (
TFS
Returns High During
Write Operation)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7713 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Loop-Powered Signal Conditioning ADC |
| AD7713AN | 功能描述:IC ADC 24BIT SIGMA-DELTA 24-DIP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD7713ANZ | 功能描述:IC ADC 24BIT SIGMA-DELTA 24-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7713AQ | 制造商:Rochester Electronics LLC 功能描述:24 BIT SIGMA DELTA ADC IC - Bulk |
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