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參數資料
| 型號： | AD7718BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| 中文描述： | 10-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數： | 29/44頁 |
| 文件大小： | 339K |
| 代理商： | AD7718BR |
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REV. 0
AD7708/AD7718
–29–
AD0C2
AD0C1
AD0C0
RN2
RN1
RN0
ADC Range Bits
Written by the user to select the ADC input range as follows
RN2
RN1
RN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Selected ADC Input Range (VREF = 2.5 V)
±
20 mV
±
40 mV
±
80 mV
±
160 mV
±
320 mV
±
640 mV
±
1.28 V
±
2.56 V
Filter Register (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 45Hex)
The Filter Register is an 8-bit register from which data can be read or to which data can be written. This register determines the
amount of averaging performed by the sinc filter. Table XVII outlines the bit designations for the Filter Register. FR7 through FR0
indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit. The number in this register is used to set the decimation factor and
thus the output update rate for the ADCs. The filter register cannot be written to by the user the ADC is active. The update rate is
used for the ADCs is calculated as follows:
f
f
CHOP Enabled CHOP
f
SF
f
CHOP Disabled CHOP
ADC
MOD
ADC
MOD
=
×
=
=
×
×
=
)
)
1
3
0
1
8
1
where
f
ADC
= ADC Output Update Rate,
f
MOD
= Modulator Clock Frequency = 32.768 kHz,
SF
= Decimal Value Written to SF Register.
Table XVII. Filter Register Bit Designations
7
R
F
6
R
F
5
R
F
4
R
F
3
R
F
2
R
F
1
R
F
0
R
F
)
0
(
7
F
S
6
F
S
)
1
(
5
F
S
)
0
(
4
F
S
)
0
(
3
F
S
)
0
(
)
1
(
2
F
S
)
0
(
1
F
S
)
1
(
0
F
S
The allowable range for SF is 13 decimal to 255 decimal with chop enabled, and the allowable SF range when chop is disabled is 03
decimal to 255 decimal. Examples of SF values and corresponding conversion rate (f
ADC
) and time (t
ADC
) are shown in Table XVIII.
It should be noted that optimum performance is obtained when operating with chop enabled. When chopping is enabled (
CHOP
= 0),
the filter register is loaded with FF HEX during a calibration cycle. With chop disabled (
CHOP
=1), the value in the filter register is
used during calibration.
Table XVIII. Update Rate vs. SF Word
CHOP Enabled
CHOP Disabled
SF (Dec)
SF (Hex)
f
ADC
(Hz)
N/A
105.3
19.79
5.35
t
ADC
(ms)
N/A
9.52
50.34
186.77
f
ADC
(Hz)
1365.33
315
59.36
16.06
t
ADC
(ms)
0.732
3.17
16.85
62.26
03
13
69
255
03
0D
45
FF
Table XVI. ADC Control Register (ADCCON) Bit Designations (continued)
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