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參數資料
| 型號： | AD7718BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| 中文描述： | 10-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數： | 31/44頁 |
| 文件大小： | 339K |
| 代理商： | AD7718BR |
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REV. 0
AD7708/AD7718
–31–
Bipolar Mode
With an analog input voltage of (–1.024 V
REF
/GAIN), the output code is 0000 Hex using the AD7708 and 000000H using the AD7718.
With an analog input voltage of 0 V, the output code is 8000Hex for the AD7708 and 800000Hex for the AD7718. With an analog
input voltage of (+1.024 V
REF
/GAIN), the output code is FFFF Hex for the AD7708 and FFFFFF Hex for the AD7718. Note the
analog inputs are pseudo bipolar inputs and the analog input voltage must remain within the common-mode input range at all times.
The output code for any analog input voltage can be represented as follows:
Code
= 2
N
–1
×
[(
AIN
×
GAIN
/1.024
×
V
REF
) + 1]
where
AIN
is the analog input voltage,
N
= 16 for the AD7708, and
N
= 24 for the AD7718.
ADC Offset Calibration Coefficient Registers (OF0): (A3, A2, A1, A0 = 0, 1, 0, 1; Power-On-Reset = 8000(00)Hex)
The offset calibration registers are 16-bit registers on the AD7708 and 24-bit registers on the AD7718. These registers hold the offset
calibration coefficient for the ADC. The power-on-reset value of the internal zero-scale calibration coefficient registers is 8000(00).
There are five offset registers available, one for each of the fully differential input channels. Calibration register pairs are shared when
operating in pseudo-differential input mode. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration is initiated by the user via MD2–MD0 bits in the MODE register. The channel bits, in association with the communication
register address for the OF0 register, allow access to this register. This register is a read/write register. The calibration register can
only be written to if the ADC is inactive (MD bits in the mode register = 000 or 001). Reading of the calibration register does not
clear the RDY bit.
ADC Gain Calibration Coefficient Register (GNO): (A3, A2, A1, A0 = 0, 1, 1, 0; Power-On-Reset = 5XXX(X5) Hex)
The gain calibration registers are 16-bit registers on the AD7708 and 24-bit registers on the AD7718. These registers are configured
at power-on with factory-calculated internal full-scale calibration coefficients. There are five full-scale registers available, one for each
of the fully differential input channels. Calibration register pairs are shared when operating in pseudo-differential input mode. Every
device will have different default coefficients. However, these bytes will be automatically overwritten if an internal or system full-scale
calibration is initiated by the user via MD2–MD0 bits in the MODE register. The channel bits, in association with the communication
register address, allow access to the data contained in the GN0 register. This is a read/write register. The calibration registers can
only be written to if the ADC is inactive (MD bits in the mode register = 000 or 001). Reading of the calibration registers does not
clear the RDY bit. A calibration (self or system) is required when operating with chop mode disabled.
ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On-Reset = 4X Hex (AD7718) and 5X Hex (AD7708)
This register is a read only 8-bit register. The contents are used to determine the die revision of the silicon. Table XX indicates the
bit locations for the AD7708.
Table XX. ID Register Bit Designation
ID4
User Nonprogrammable Test Registers
The AD7708 and AD7718 contain two test registers. The bits in these test registers control the test modes of these ADCs which are
used for the testing of the device.
The user is advised not to change the contents of these registers
.
ID7
ID6
ID5
ID3
ID2
ID1
ID0
0
1
0
0/1
X
X
X
X
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