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參數資料
| 型號： | AD7720BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS Sigma-Delta Modulator |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁數： | 6/16頁 |
| 文件大小： | 232K |
| 代理商： | AD7720BRU |
AD7720
–6–
REV. 0
PIN FUNCT ION DE SCRIPT IONS
Pin No.
Mnemonic
Function
1
REF2
Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used
to drive the sigma-delta modulator. When REF2 is used as an input, REF1 must be con-
nected to AGND.
Ground reference point for analog circuitry.
No Connect.
Standby, Logic Input. When ST BY is high, the device is placed in a low power mode.
When ST BY is low, the device is powered up.
Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from
the AD7720 is an accurate digital representation of the analog voltage at the input to the
sigma-delta modulator. T he DVAL pin is set low for 20 MCLK cycles if the analog input is
overranged.
Ground reference for the digital circuitry.
Digital Control Input. When GC is high, the gain error of the modulator can be calibrated.
Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A
logic high selects bipolar mode.
Digital Control Input. When MZERO is high, the modulator inputs are internally grounded,
i.e., tied to AGND in unipolar mode and REF2 in bipolar mode. MZERO allows on-chip
offsets to be calibrated out. MZERO is low for normal operation.
Modulator Bit Stream. T he digital bit stream from the sigma-delta modulator is output at
DAT A.
Serial Clock, Logic Output. T he bit stream from the modulator is valid on the rising edge
of SCLK .
Reset Logic Output. T he signal applied to the RESET pin is made available as an output at
RESET O.
CMOS Logic Clock Input. T he X T AL1/MCLK pin interfaces the device’s internal oscillator
circuit to an external crystal or an external clock. A parallel resonant, fundamental-frequency,
microprocessor-grade crystal and a 1 M
resistor should be connected between the MCLK
and X T AL pins with two capacitors connected from each pin to ground. Alternatively, the
X T AL1/MCLK pin can be driven with an external CMOS-compatible clock. T he part is
specified with a 12.5 MHz master clock.
Oscillator Output. T he X T AL2 pin connects the internal oscillator output to an external
crystal. If an external clock is used, X T AL2 should be left unconnected.
Digital Supply Voltage, +5 V
±
5%.
Analog Input. In unipolar operation, the analog input range on VIN(+) is VIN(–) to
(VIN(–) + V
REF
); for bipolar operation, the analog input range on VIN+ is (VIN(–)
±
V
REF
/2).
T he absolute analog input range must lie between 0 and AVDD. T he analog input is con-
tinuously sampled and processed by the analog modulator.
Analog Positive Supply Voltage, +5 V
±
5%.
Reset Logic Input. RESET is an asynchronous input. When RESET is taken high, the
sigma-delta modulator is reset by shorting the integrator capacitors in the modulator. DVAL
goes low for 20 MCLK cycles while the modulator is being reset.
Reference Input/Output. REF1 connects via a 3 k
resistor to the output of the internal
2.5 V reference, and to the input of a buffer amplifier that drives the sigma-delta modulator.
T his pin can also be overdriven with an external 2.5 V reference.
2, 14, 18, 20, 24, 26
3, 13
4
AGND
NC
ST BY
5
DVAL
6, 15
7
8
DGND
GC
BIP
9
MZERO
10
DAT A
11
SCLK
12
RESET O
16
X T AL1/MCLK
17
X T AL2
19
21, 23
DVDD
VIN(–), VIN(+)
25, 28
22
AVDD
RESET
27
REF1
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相關代理商/技術參數 |
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| AD7720BRU-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 25Msps 16-bit Serial 28-Pin TSSOP T/R |
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