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參數資料
| 型號： | AD7724 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual CMOS Modulators |
| 中文描述： | 調制器雙通道CMOS |
| 文件頁數： | 12/14頁 |
| 文件大小： | 552K |
| 代理商： | AD7724 |
REV. A
AD7724
–12–
Input Circuits
Figures 28 and 29 show two simple circuits for bipolar mode
operation. Both circuits accept a single-ended bipolar signal
source and create the necessary differential signals at the input
to the ADC.
The circuit in Figure 28 creates a 0 V to 2.5 V signal at the
VIN(+) pins to form a differential signal around an initial bias
voltage of 1.25 V. For single-ended applications, best THD
performance is obtained with VIN(–) set to 1.25 V rather than
2.5 V. The input to the AD7724 can also be driven differen-
tially with a complementary input as shown in Figure 29.
In this case, the input common-mode voltage is set to 2.5 V.
The 2.5 V p-p full-scale differential input is obtained with a
1.25 V p-p signal at each input in antiphase. This configuration
minimizes the required output swing from the amplifier circuit
and is useful for single supply applications.
12pF
1k
V
1k
V
1/2
OP275
+
AIN =
1.25V
–
12pF
1k
V
110nF
R
1nF
VIN(–)
VIN(+)
REF1
REF2
110nF
DIFFERENTIAL
INPUT = 2.5V p-p
VIN(–) BIAS
VOLTAGE = 2.5V
OP07
R
1nF
+
–
1/2
+
–
1k
V
Figure 28. Single-Ended Analog Input for Bipolar Mode
Operation
12pF
1k
V
AIN =
6
0.625V
1k
V
1k
V
12pF
1k
V
1/2
OP275
110nF
R
R
1nF
VIN(–)
1nF
1/2
OP275
VIN(+)
DIFFERENTIAL
INPUT = 2.5V p-p
COMMON-MODE
VOLTAGE = 2.5V
REF1
OP07
REF2
110nF
Figure 29. Single-Ended-to-Differential Analog Input
Circuit for Bipolar Mode Operation
The 1 nF capacitors at each input store charge to aid the
amplifier settling as the input is continuously switched. A
resistor in series with the drive amplifier output and the 1 nF
input capacitor may also be used to create an antialias filter.
Clock Generation
The AD7724 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. The connection diagram for use with the crystal is shown
in Figure 30. Consult the crystal manufacturer's recommenda-
tion for the load capacitors.
1M
V
XTAL
MCLK
Figure 30. Crystal Oscillator Connection
An external clock must be free of ringing and have a minimum
rise time of 5 ns. Degradation in performance can result as high
edge rates increase coupling that can generate noise in the sam-
pling process. The connection diagram for an external clock
source (Figure 31) shows a series damping resistor connected
between the clock output and the clock input to the AD7724.
The optimum resistor will depend on the board layout and the
impedance of the trace connecting to the clock input.
CLOCK
CIRCUITRY
MCLK
25–150
V
Figure 31. External Clock Oscillator Connection
A low phase clock should be used to generate the ADC sam-
pling clock because sampling clock jitter effectively modulates
the input signal and raises the noise floor. The sampling clock
generator should be isolated from noisy digital circuits, grounded
and heavily decoupled to the analog ground plane.
A sine wave can also be used to provide the clock (Figure 32.) A
sine wave with a voltage swing between 0.4 V p-p and 4 V p-p is
needed. XTAL_OFF is tied low and a 1 M
resistor is needed
between XTAL1 and XTAL2. A 22 pF capacitor is connected
in parallel with this resistor. The sine wave is ac coupled to
XTAL1 using a 120 pF capacitor. The use of a sine wave to
generate the clock eliminates the need for a square wave clock
source which introduces noise.
1M
V
XTAL1
XTAL2
XTAL_OFF
22pF
SINEWAVE
INPUT
120pF
Figure 32. Using a Sine Wave Input as a Clock Source
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