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參數資料
| 型號： | AD7725BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit 900 kSPS ADC with a Programmable Postprocessor |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, MS-022-AB, MQFP-44 |
| 文件頁數： | 11/28頁 |
| 文件大小： | 442K |
| 代理商： | AD7725BS |
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REV. A
AD7725
–11–
Pin No.
Mnemonic S/P
Description
27
STBY
Standby, Logic Input. When STBY is taken high, the device will enter a low power mode.
If the device was fully configured before entering this mode, it will not lose its configuration data.
When STBY is brought low, the device exits the low power mode. If the device
was partially configured before entering the low power mode, it will restart the configuration
process in the case of boot from ROM (BFR) mode, DSP mode, and EPROM mode or, in
parallel mode, a new configure instruction must be issued to configure the device. If the device
was fully configured before entering the low power mode, it will continue to output conversion
results in all serial modes; in parallel mode, the device will wait for an instruction to begin
converting. In STBY mode, the clock input must be continual.
Ground Reference for Digital Circuitry.
Synchronization Logic Input. When using more than one AD7725 operated from a
common master clock, SYNC allows each ADC to simultaneously sample its analog input
and update its output register. When SYNC is high, the digital filter sequencer counter is
reset to zero and the postprocessor core is reset. Because the digital filter and sequencer
are completely reset during this action, SYNC pulses cannot be applied continuously.
When SYNC is taken low, normal conversions continue, with valid data resulting after the
filter setting time.
Serial Mode.
SOE
–Serial Output Enable. In EPROM mode,
SOE
going low enables the
external EPROM and is used to reset the EPROM’s address counter. In DSP mode,
SOE
is an
active high interrupt. It goes high after a power-on reset and after a pulse on the
RESETCFG
pin, indicating the device is ready to be configured. It also goes high following a successful
configuration, indicating that the device was configured correctly.
SOE
is reset low when FSI
is detected high by CLKIN. In BFR
mode,
SOE
pulses high for eight CLKIN cycles at the end
of a successful configuration.
Parallel Mode
.
CS
–Chip Select Logic Input. This is an active low logic input used in
conjunction with the RD/
WR
input to read data from or write data to the device. For a
read operation, the falling edge of
CS
takes the bus out of three-state and either the
conversion data or the status register data (depending on the state of the RS input), is
placed onto the data bus, after the time t
. For a write operation, the rising edge of
CS
is used to latch either the configuration data or the instruction (depending on the state of
the RS input) into the AD7725. In this case, the data should be set up for a time t
25
before
the
CS
rising edge.
Serial Mode
. SMODE1–Serial Mode Select, Logic Input. This pin selects the serial mode to
be used (see Table IV) and thus informs the device where to download configuration data from
automatically on power up. To change the value on this pin, a full power cycle
needs to be performed.
Parallel Mode
. DB15–Data Input/Output Bit (MSB).
Serial Mode
. SMODE0–Serial Mode Select, Logic Input. This pin selects the serial mode to
be used (see Table IV) and thus informs the device where to download configuration data
from automatically on power-up. To change the value on this pin, a full power cycle needs to
be performed.
Parallel Mode
. DB14–Data Input/Output Bit.
Serial Mode
. SCR–Serial Clock Rate Select, Logic Input. With SCR set to logic low,
the serial clock output frequency, SCO, is equal to the CLKIN frequency. A logic high
sets the frequency of SCO to one half the CLKIN frequency.
Parallel Mode
. DB13–Data Input/Output Bit.
Serial Mode
. CFGEND–Configuration End, Logic Output. A logic high on CFGEND
indicates that device programming is complete and no programming errors occurred.
Parallel Mode
. DB12–Data Input/Output Bit.
Serial Mode
. DGND–Digital Ground.
Parallel Mode
. DB11–Data Input/Output Bit.
Serial Mode
. DGND–Digital Ground.
Parallel Mode
. DB10–Data Input/Output Bit.
Serial Mode
. FSO–Frame Synchronization Output. FSO indicates the beginning of a
word transmission on the SDO pin. The FSO signal is a positive pulse approximately
one SCO period wide.
Parallel Mode
. DB9–Data Input/Output Bit.
28
29
DGND
SYNC
30
SOE
/
CS
31
SMODE1/DB15
32
SMODE0/DB14
33
SCR/DB13
34
CFGEND/DB12
35
DGND/DB11
36
DGND/DB10
37
FSO/DB9
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