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參數資料
| 型號： | AD7725BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit 900 kSPS ADC with a Programmable Postprocessor |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, MS-022-AB, MQFP-44 |
| 文件頁數： | 13/28頁 |
| 文件大小： | 442K |
| 代理商： | AD7725BS |
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REV. A
AD7725
–13–
TERMINOLOGY
Integral Nonlinearity (INL)
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be
confused with bipolar zero), a point 0.5 LSB below the first
code transition (100 . . . 00 to 100 . . . 01 in bipolar mode,
000 . . . 00 to 000 . . . 01 in unipolar mode) and full scale, a
point 0.5 LSB above the last code transition (011 . . . 10 to
011 . . . 11 in bipolar mode, 111 . . . 10 to 111 . . . 11 in
unipolar mode). The error is expressed in LSBs.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal
1 LSB change between two adjacent codes in the ADC.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal V
(+) voltage, which is (V
IN
(–) + 0.5 LSB) when
operating in the unipolar mode.
Bipolar Offset Error
This is the deviation of the midscale transition code
(111 . . . 11 to 000 . . . 00) from the ideal V
(+) voltage,
which is (V
IN
(–) – 0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value
0.5 LSB above negative full scale. The last code transition
should occur for an analog value 1.5 LSB below the nominal
full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all of the nonfundamental signals up
to
half the output data rate (f
O
/2), excluding dc. The ADC is
evaluated by applying a low noise, low distortion sine wave
signal to the input pins. By generating a Fast Fourier Trans-
form (FFT) plot, the SNR data can then be obtained from the
output spectrum.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the rms
value of the fundamental. THD is defined as
THD
=
+
+
+
+
20
log
V
V
V
V
V
V
2
2
3
2
4
2
5
2
6
2
1
where
V
is the rms amplitude of the fundamental and
V
,
V
3
,
V
4
,
V
5
, and
V
6
are the rms amplitudes of the second through
sixth harmonics.
Spurious Free Dynamic Range (SFDR)
Defined as the difference, in dB, between the peak spurious or
harmonic component in the ADC output spectrum (up to
f
/2 and excluding dc) and the rms value of the fundamental.
Normally, the value of this specification will be determined by
the largest harmonic in the output spectrum of the FFT. For
input signals whose second harmonics occur in the stop band
region of the digital filter, the spur in the noise floor limits
the SFDR.
Settling Time and Group Delay
The settling time of a digital filter is dependent on the amount
of decimation employed and the number of filter taps used in
the filter design and is calculated as follows:
settling time
data input rate
number of taps
=
×
1
The settling time for each filter stage should be calculated
separately and then added to get the total filter settling time.
Group delay is half the settling time.
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