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參數資料
| 型號： | AD7730BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH 19-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數： | 10/52頁 |
| 文件大小： | 497K |
| 代理商： | AD7730BN |
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AD7730/AD7730L
–10–
REV. A
OUT PUT NOISE AND RE SOLUT ION SPE CIFICAT ION
T he AD7730 can be programmed to operate in either chop mode or nonchop mode. T he chop mode can be enabled in ac-excited or
dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. T hese
options are discussed in more detail in later sections. T he chop mode has the advantage of lower drift numbers and better noise im-
munity, but the noise is approximately 20% higher for a given –3 dB frequency and output data rate. It is envisaged that the majority
of weigh-scale users of the AD7730 will operate the part in chop mode to avail themselves of the excellent drift performance and
noise immunity when chopping is enabled. T he following tables outline the noise performance of the part in both chop and nonchop
modes over all input ranges for a selection of output rates. Settling time refers to the time taken to get an output that is 100% settled
to new value.
Output Noise (CHP = 1)
T his mode is the primary mode of operation of the device. T able I shows the output rms noise for some typical output update rates
and –3 dB frequencies for the AD7730 when used in chopping mode (CHP of Filter Register = 1) with a master clock frequency of
4.9152 MHz. T hese numbers are typical and are generated at a differential analog input voltage of 0 V. T he output update rate is
selected via the SF0 to SF11 bits of the Filter Register. T able II, meanwhile, shows the output peak-to-peak resolution in counts for
the same output update rates. T he numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5
LSB). It is important to note that the numbers in T able II represent the resolution for which there will be no code flicker within a
six-sigma limit. T hey are not calculated based on rms noise, but on peak-to-peak noise.
T he numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in T able I will remain the same for unipolar ranges while the
numbers in T able II will change. T o calculate the numbers for T able II for unipolar input ranges simply divide the peak-to-peak
resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.
T able I. Output Noise vs. Input Range and Update Rate (CHP = 1)
T ypical Output RMS Noise in nV
Output
Data Rate Frequency
–3 dB
SF
Word
Settling T ime
Normal Mode
Settling T ime
Fast Mode
Input Range
=
6
80 mV
Input Range
=
6
40 mV
Input Range
=
6
20 mV
Input Range
=
6
10 mV
50 Hz
100 Hz
150 Hz
200 Hz*
400 Hz
1.97 Hz
3.95 Hz
5.92 Hz
7.9 Hz
15.8 Hz
2048
1024
683
512
256
460 ms
230 ms
153 ms
115 ms
57.5 ms
60 ms
30 ms
20 ms
15 ms
7.5 ms
115
155
200
225
335
75
105
135
145
225
55
75
95
100
160
40
60
70
80
110
*Power-On Default
T able II. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1)
Peak-to-Peak Resolution in Counts (Bits)
Output
Data Rate Frequency
–3 dB
SF
Word
Settling T ime
Normal Mode
Settling T ime
Fast Mode
Input Range
=
6
80 mV
Input Range
=
6
40 mV
Input Range
=
6
20 mV
Input Range
=
6
10 mV
50 Hz
100 Hz
150 Hz
200 Hz*
400 Hz
1.97 Hz
3.95 Hz
5.92 Hz
7.9 Hz
15.8 Hz
2048
1024
683
512
256
460 ms
230 ms
153 ms
115 ms
57.5 ms
60 ms
30 ms
20 ms
15 ms
7.5 ms
230k (18)
170k (17.5)
130k (17)
120k (17)
80k (16.5)
175k (17.5)
125k (17)
100k (16.5)
90k (16.5)
55k (16)
120k (17)
90k (16.5)
70k (16)
65k (16)
40k (15.5)
80k (16.5)
55k (16)
45k (15.5)
40k (15.5)
30k (15)
*Power-On Default
Output Noise (CHP = 0)
T able III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730 when used in non-
chopping mode (CHP of Filter Register = 0) with a master clock frequency of 4.9152 MHz. T hese numbers are typical and are gen-
erated at a differential analog input voltage of 0 V. T he output update rate is selected via the SF0 to SF11 bits of the Filter Register.
T able IV, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. T he numbers in brackets
are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB). It is important to note that the numbers in T able
IV represent the resolution for which there will be no code flicker within a six-sigma limit. T hey are not calculated based on rms
noise, but on peak-to-peak noise.
T he numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in T able III will remain the same for unipolar ranges while the
numbers in T able IV will change. T o calculate the number for T able IV for unipolar input ranges simply divide the peak-to-peak
resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.
相關PDF資料 |
PDF描述 |
|---|---|
| AD7730BR | Bridge Transducer ADC |
| AD7730BRU | Bridge Transducer ADC |
| AD7730L | Bridge Transducer ADC |
| AD7731 | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BN | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7730BNZ | 功能描述:IC ADC TRANSDUCER BRIDGE 24-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BR | 功能描述:IC ADC BRIDGE TRANSDUCER 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BR-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BR-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BRU | 功能描述:IC ADC BRIDGE TRANSDUCER 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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