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參數(shù)資料
| 型號(hào)： | AD7730BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH 19-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁(yè)數(shù)： | 9/52頁(yè) |
| 文件大?。?/td> | 497K |
| 代理商： | AD7730BN |
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AD7730/AD7730L
REV. A
–9–
Pin
No.
Mnemonic
Function
18
STANDBY
Logic Input. T aking this pin low shuts down the analog and digital circuitry, reducing current consumption to
the 5
μ
A range. T he on-chip registers retain all their values when the part is in standby mode.
Chip Select. Active low Logic Input used to select the AD7730. With this input hardwired low, the AD7730
can operate in its three-wire interface mode with SCLK , DIN and DOUT used to interface to the device.
CS
can be used to select the device in systems with more than one device on the serial bus or as a frame synchro-
nization signal in communicating with the AD7730.
Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a
logic low on this output indicates that a new output word is available from the AD7730 data register. T he
RDY
pin will return high upon completion of a read operation of a full output word. If no data read has taken
place after an output update, the
RDY
line will return high prior to the next output update, remain high while
the update is taking place and return low again. T his gives an indication of when a read operation should not
be initiated to avoid initiating a read from the data register as it is being updated. In calibration mode,
RDY
goes high when calibration is initiated and it returns low to indicate that calibration is complete. A number of
different events on the AD7730 set the
RDY
high and these are outlined in T able X VIII.
Serial Data Output with serial data being read from the output shift register on the part. T his output shift
register can contain information from the calibration registers, mode register, status register, filter register,
DAC register or data register, depending on the register selection bits of the Communications Register.
Serial Data Input with serial data being written to the input shift register on the part. Data from this input
shift register is transferred to the calibration registers, mode register, communications register, DAC register
or filter registers depending on the register selection bits of the Communications Register.
Digital Supply Voltage, +3 V or +5 V nominal.
Ground reference point for digital circuitry.
19
CS
20
RDY
21
DOUT
22
DIN
23
24
DV
DD
DGND
T E RMINOLOGY
INT E GRAL NONLINE ARIT Y
T his is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. T he end-
points of the transfer function are zero scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). T he
error is expressed as a percentage of full scale.
POSIT IVE FULL-SCALE E RROR
Positive Full-Scale Error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage
(AIN(–) + V
REF
/GAIN – 3/2 LSBs). It applies to both unipolar
and bipolar analog input ranges. Positive full-scale error is a
summation of offset error and gain error.
UNIPOLAR OFFSE T E RROR
Unipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
BIPOLAR ZE RO E RROR
T his is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB)
when operating in the bipolar mode.
GAIN E RROR
T his is a measure of the span error of the ADC. It is a measure
of the difference between the measured and the ideal span be-
tween any two points in the transfer function. T he two points
used to calculate the gain error are full scale and zero scale.
BIPOLAR NE GAT IVE FULL-SCALE E RROR
T his is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – V
REF
/GAIN + 0.5 LSB) when operat-
ing in the bipolar mode. Negative full-scale error is a summation
of zero error and gain error.
POSIT IVE FULL-SCALE OVE RRANGE
Positive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages on AIN(+) input greater than
AIN(–) + V
REF
/GAIN (for example, noise peaks or excess volt-
ages due to system gain errors in system calibration routines) with-
out introducing errors due to overloading the analog modulator
or overflowing the digital filter.
NE GAT IVE FULL-SCALE OVE RRANGE
T his is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – V
REF
/GAIN without overloading the
analog modulator or overflowing the digital filter.
OFFSE T CALIBRAT ION RANGE
In the system calibration modes, the AD7730 calibrates its
offset with respect to the analog input. T he Offset Calibration
Range specification defines the range of voltages the AD7730
can accept and still accurately calibrate offset.
FULL-SCALE CALIBRAT ION RANGE
T his is the range of voltages that the AD7730 can accept in the
system calibration mode and still calibrate full scale correctly.
INPUT SPAN
In system calibration schemes, two voltages applied in sequence
to the AD7730’s analog input define the analog input range.
T he input span specification defines the minimum and maxi-
mum input voltages, from zero to full scale, the AD7730 can
accept and still accurately calibrate gain.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7730BR | Bridge Transducer ADC |
| AD7730BRU | Bridge Transducer ADC |
| AD7730L | Bridge Transducer ADC |
| AD7731 | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BN | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7730BNZ | 功能描述:IC ADC TRANSDUCER BRIDGE 24-DIP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BR | 功能描述:IC ADC BRIDGE TRANSDUCER 24-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BR-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BR-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BRU | 功能描述:IC ADC BRIDGE TRANSDUCER 24TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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