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參數資料
| 型號： | AD7732BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, +-10 V Input Range, High Throughput, 24-Bit SIGMA- ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁數： | 18/32頁 |
| 文件大小： | 1576K |
| 代理商： | AD7732BRU |
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AD7732
Channel Zero-Scale Calibration Registers
24 Bits, Read/Write Registers, Address 10h, 12h, Default Value
800000h
These registers hold the particular channel zero-scale
calibration coefficients. The value in these registers is used in
conjunction with the value in the corresponding channel full-
scale calibration register, the ADC zero-scale calibration
register, and the ADC full-scale register to digitally scale the
particular channel conversion results. The value in this register
is updated automatically following the execution of a channel
zero-scale system calibration.
The format of the channel zero-scale calibration register is a
sign bit and 22 bits unsigned value. Writing this register is
possible in the idle mode only (see the Calibration section for
more details).
Channel Full-Scale Calibration Registers
24 Bits, Read/Write Registers, Address 18h, 1Ah, Default Value
200000h
These registers hold the particular channel full-scale calibration
coefficients. The value in these registers is used in conjunction
with the value in the corresponding channel zero-scale
calibration register, the ADC zero-scale calibration register, and
the ADC full-scale register to digitally scale the particular
channel conversion results. The value in this register is updated
automatically following the execution of a channel full-scale
system calibration. Writing this register is possible in the idle
mode only (see the Calibration section for more details).
Channel Status Registers
8 Bits, Read-Only Register, Address 20h, 22h, Default Value 20h × Channel Number
These registers contain individual channel status information and some general AD7732 status information. Reading the status registers
can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data
registers in the continuous read mode (see the Digital Interface Description section for more details).
Bit
Mnemonic
Default
Bit 7
0
Bit 6
CH1
Bit 5
0
Bit 4
0/P0
0
Bit 3
RDY/P1
0
Bit 2
NOREF
0
Bit 1
SIGN
0
Bit 0
OVR
0
Channel Number
Bit
7–5
Mnemonic
CH1
Description
These bits reflect the channel number. This can be used for current channel identification and easier
operation of the dump mode and continuous read mode.
When the status option bit of the corresponding channel setup register is reset to 0, this bit is read as a zero.
When the status option bit is set to 1, this bit reflects the state of the P0 pin, whether it is configured as an
input or an output.
When the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the
selected channel RDY bit in the ADC status register. When the status option bit is set to 1, this bit reflects the
state of the P1 pin, whether it is configured as an input or an output.
This bit indicates the reference input status. If the voltage between the REFIN(+) and REFIN(–) pins is less than
NOREF, the trigger voltage and a conversion is executed, then the NOREF bit goes to 1.
The voltage polarity at the analog input. It will be 0 for a positive voltage and 1 for a negative voltage.
This bit reflects either the overrange or the underrange on the analog input. The bit is set to 1 when the
analog input voltage goes over or under the nominal voltage range (see the Analog Input’s Extended Voltage
Range section).
4
0/P0
3
RDY/P1
2
NOREF
1
0
SIGN
OVR
Rev. 0 | Page 18 of 32
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