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參數(shù)資料
| 型號： | AD7732BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, +-10 V Input Range, High Throughput, 24-Bit SIGMA- ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 1576K |
| 代理商： | AD7732BRU |
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AD7732
Parameter
DV
DD
Current (Normal Mode)
14
Power Dissipation (Normal Mode)
14
AV
DD
+DV
DD
Current (Standby Mode)
15
Power Dissipation (Standby Mode)
15
Rev. 0 | Page 5 of 32
Min
Typ
1.0
85
140
750
Max
1.5
100
Unit
mA
mW
μA
μW
Test Conditions/Comments
DV
DD
= 3 V
1
Specifications are not production tested but guaranteed by design and/or characterization data at initial product release.
2
See Typical Performance Characteristics.
3
V
CM
= Common-Mode Voltage = 0 V.
4
Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.
5
Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error.
6
ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise.
7
For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage
range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register
value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details.
8
The AIN absolute voltage of ±16.5 V applies for a nominal VBIAS voltage of +2.5 V. By configuring the BIAS and RA to RD pins differently, the part will work with higher
AIN absolute voltages as long as the internal voltage seen by the multiplexer and the input buffer is within 200 mV to AV
DD
– 300 mV. Absolute voltage for the AIN,
BIAS, and RA to RD pins must never exceed the values specified in the Absolute Maximum Ratings.
9
Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 k + 15.5 k = 124 k.
10
For specified performance. Part is functional with lower V
REF
.
11
Dynamic current charging the sigma-delta modulator input switching capacitor.
12
Outside the specified calibration range, calibration is possible but the performance may degrade.
13
These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
14
With external MCLK, MCLKOUT is disabled (the CLKDIS bit is set in the m
ode register).
15
External MCLKIN = 0 V or DV
DD
, Digital Inputs = 0 V or DV
DD
, and P0 and P1 = 0 V or AV
DD.
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相關代理商/技術參數(shù) |
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