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參數資料
| 型號： | AD773AJD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 20 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數： | 8/16頁 |
| 文件大小： | 223K |
| 代理商： | AD773AJD |
AD773A
REV. 0
–8–
RE FE RE NCE INPUT
T he AD773A’s high impedance reference input allows direct
connection with standard voltage references. Unlike the resistor
ladder requirements of a flash converter the AD773A’s single
pin, high impedance input can be driven from one low cost, low
power reference. T he high impedance input allows multiple
AD773A’s to be driven from one reference thus minimizing drift
errors.
Figure 11 shows the AD773A connected to the AD680. T he
AD680 is a single supply, low power, low cost 2.5 V reference
with performance specifications ideally suited for the AD773A.
T he low pass filter minimizes the AD680’s wideband noise.
Other recommended 2.5 V references are the AD580 and
REF43.
AD680
2
GND
4
V
V
OUT
6
REF IN
REF GND
22
10
μ
F
0.1
μ
F
AD773A
2
1
Figure 11. Recommended AD773A to AD680 Connection
CLOCK INPUT
T he AD773A’s pipelined architecture operates on both the
rising and falling edges of the clock input. A low jitter,
symmetrical clock will provide the highest level of performance.
T he recommended logic family to drive the clock input is HC.
T he AD773A’s minimum clock half cycle may necessitate the
use of an external divide-by-two circuit as shown in Figure 12.
Power dissipation will vary with input clock frequency as shown
in Figure 13.
+5V
R
D
74XX74
Q
Q
S
40MHz
+5V
CLK
Figure 12. Divide-by-Two Clock Circuit
1.07
1.04
1.02
1.0E+07
1.03
1.06
1.05
SAMPLE FREQUENCY – Hz
P
1.5E+07
2.0E+07
1.08
Figure 13. Power Dissipation vs. Sample Frequency
E QUIVALE NT ANALOG INPUT CIRCUIT
T he AD773A equivalent analog input circuit is shown in Figure
14. T he typical input bias current is 5
μ
A, while input
capacitance is typically 5 pF. In the single-ended input
configuration one input is connected to AGND while the
second input is driven to full scale (
±
500 mV). Under nominal
conditions the collector of the input transistor is at +1.15 V.
T his allows signals to be offset by up to +0.65 V without
significantly degrading performance. In the negative direction,
the emitter of the input transistor should not drop below
–1.25 V. T herefore, signals can be offset by –0.65 V without
significant performance degradation. Figure 15 shows
signal-to-noise ratio vs. common-mode input voltage.
+5V
1.0mA
+1.15V
1.0mA
–5V
–1.25V
5pF
AIN
1Vp-p
AD773A
Figure 14. Equivalent Analog Input Circuit
60
0
30
10
20
50
40
S
AIN = –0.3dB
AIN = – 6dB
COMMON MODE INPUT VOLTAGE – V
1.0
–1.2
–1.4
0.8
0.4
0.2
0.0
0.6
–0.4
–0.6
–0.8
–1.0
–0.2
Figure 15. S/N+D vs. Common-Mode Input Voltage,
f
CLK
= 20 MSPS
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PDF描述 |
|---|---|
| AD773AKD | 10-Bit, 20 MSPS Monolithic A/D Converter |
| AD7740KRM | 3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter |
| AD7740YRT | 3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter |
| AD7740 | 3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD773AKD | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 20 MSPS Monolithic A/D Converter |
| AD773ASD/883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
| AD773-EB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD773JD | 制造商:Analog Devices 功能描述: |
| AD773KD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
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