
AD773A
REV. 0
–9–
E QUIVALE NT RE FE RE NCE INPUT CIRCUIT
T he AD773A is designed to have a reference to analog input
voltage ratio of 2.5:1. When the AD773A is configured for
single-ended operation a 2.5 volt reference input establishes a
full-scale analog input voltage of 1 V p-p (
±
500 mV with respect
to V
INB
). Although the AD773A is specified and tested with
V
REF
equal to 2.5 V and V
IN
equal to
±
500 mV the reference
input voltage and analog input voltages can be changed. T o
optimize the AD773A’s performance the 2.5:1 ratio should be
maintained. T he simplified model of the AD773A’s reference
input circuit is shown in Figure 16.
REFIN
REFGND
R3
R1
R2
V
–5V
A
BIAS
AD773A
Figure 16. Typical Reference Input Circuit
T he 2.5 V external reference is applied across resistor R1
producing a current which in turn generates a voltage V
BIAS
.
Multiple reference currents are generated from V
BIAS
and are
used throughout the converter. R3 is used to cancel errors
induced by the input bias current of the REFGND buffer.
Figure 17 shows the SNR performance as the reference voltage
is varied from its nominal value of 2.5 V. T he input full-scale
voltage is defined by the following equation,
Input Full-Scale Voltage =
T he power dissipation is modulated by variations in the
reference voltage. Figure 18 shows the variation in power
dissipation versus reference voltage.
ReferenceVoltage
2.5
60
30
45
35
40
55
50
1.0
3.8
3.0
2.6
2.2
1.8
REFERENCE INPUT VOLTAGE – V
1.4
3.4
S
AIN = –0.3dB
AIN = –6dB
Figure 17. S/N+D vs. Reference Input Voltage,
f
CLK
= 20 MSPS, f
IN
= 1 MHz
1.2
0.9
3.0
1.1
1
2
REFIN – V
P
2.6
2.4
2.2
2.8
2.7
2.5
2.3
2.1
2.9
Figure 18. Power Dissipation vs. Reference Input
Voltage, f
CLOCK
= 20 MSPS
T RANSIE NT RE SPONSE
T he fast settling input T HA accurately converts full-scale input
voltage swings in under one clock cycle. T he T HA’s high
impedance, fast slewing performance is critical in multiplexed or
dc stepped (charge coupled devices, infrared detectors) systems.
Figure 19 show the AD773A’s settling performance with an
input signal stepped from –500 mV to 0 V. As can be seen, the
output code settles to its final value in under one clock cycle.
0
0
TIME – ns
C
40
600
200
10
400
1000
800
30
20
CODE
Figure 19. Typical AD773A Settling Time