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| 型號(hào)： | AD7769JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | LC2MOS Analog I/O Port |
| 中文描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大小： | 265K |
| 代理商： | AD7769JP |
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REV. A
–2–
AD7769–SPECIFICATIONS
ADC SPECIFICATIONS
Parameter
J Version
A Version
Units
Conditions/Comments
DC ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
+25
°
C
T
MIN
to T
MAX
Bias Offset Match
+25
°
C
T
MIN
to T
MAX
Plus or Minus Full-Scale Error
+25
°
C
T
MIN
to T
MAX
Plus or Minus Full-Scale Match
+25
°
C
T
MIN
to T
MAX
ADC T O DAC MAT CHING
Bias Offset Match
+25
°
C
T
MIN
to T
MAX
Plus or Minus Full-Scale Match
+25
°
C
T
MIN
to T
MAX
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio (SNR)
T otal Harmonic Distortion (T HD) 48
Intermodulation Distortion (IMD) 60
Frequency Response
8
±
1
±
1
*
*
*
Bits
LSB max
LSB max
See T erminology
No Missing Codes. See T erminology.
See T erminology
±
2.5
±
3.0
*
*
LSB max
LSB max
Channel A to Channel B
±
2.5
±
3.5
*
*
LSB max
LSB max
See T erminology
±
2.0
±
2.5
*
*
LSB max
LSB max
Channel A to Channel B
±
3.5
±
4
*
*
LSB max
LSB max
Channel A/B to V
OUT
A/B
V
BIAS
(DAC) = +5 V, V
SWING
(DAC) = +2.5 V.
±
2.5
±
3.5
*
*
LSB max
LSB max
±
3.5
±
4.0
*
*
LSB max
LSB max
44
*
*
*
*
dB min
dB max
dB typ
dB typ
V
IN
= 100 kHz Full-Scale Sine Wave with f
SAMPLING
= 400 kHz
V
IN
= 100 kHz Full-Scale Sine Wave with f
SAMPLlNG
= 400 kHz
f
a
= 99 kHz, f
b
= 96.7 kHz with f
SAMPLING
= 400 kHz
V
IN
= Full-Scale, dc to 200 kHz Sine Wave
0.1
ANALOG INPUT S
Input Voltage Ranges, V
IN
A, V
IN
B
V
BIAS
– V
SWING
or 0
V
BIAS
+ V
SWING
or 9.8
±
0.4
V min
V max
mA max
Whichever Is the Higher
Whichever Is the Lower
Input Currents, I
IN
A, I
IN
B
ADC REFERENCE INPUT S
Input Voltage Levels
V
BIAS
(ADC)
V
SWING
(ADC)
Input Currents
V
BIAS
(ADC) Input
V
SWING
(ADC) Input
LOGIC OUT PUT S
DB0–DB7,
INT
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
DB0–DB7
Floating State Leakage Current
Floating State Capacitance
2
Output Coding
*
2/6.8
2.0/3.0
*
*
V min/max
V min/max
With Respect to AGND (ADC). For Specified Performance.
With Respect to AGND (ADC). For Specified Performance.
±
800
±
1
*
*
μ
A max
μ
A max
0.4
4.0
*
*
V max
V min
I
SINK
= 1.6 mA
I
SOURCE
= 200
μ
A
±
10
10
Offset Binary
*
*
μ
A max
pF max
POWER REQUIREMENT S
V
CC
Range
4.75/5.25
*
V min/V max
For Specified Performance. T he Part Will Function with
V
CC
=5 V
±
10% with Degraded Performance.
For Specified Performance
For ADC and DAC: V
BIAS
= 5.0 V; V
SWING
= 3.0 V; V
IN
A,
V
BIAS
; DAC Code = FF (Hex); DACA and DACB Load = 5 k
to AGND (DAC). T ypically I
DD
= 14 mA.
Logic Inputs = 2.4 V, CLK Input = 0.8 V. T ypically I
CC
= 1.5 mA.
V
DD
Range
I
DD
@ +25
°
C
V
UB
Am V
IN
B = T
MIN
to T
MAX
10.8/13.2
20
22
*
*
*
V min/V max
mA max
mA max
I
CC
@ +25
°
C
T
MIN
to T
MAX
5
6
*
*
mA max
mA max
NOT ES
1
T emperature range as follows: J Version: 0
°
C to +70
°
C; A Version: –40
°
C to +85
°
C.
2
Sample tested at +25
°
C to ensure compliance.
*Specification same as J Version.
Specifications subject to change without notice.
(V
DD
= +12 V
6
10%; V
CC
= +5 V
6
5%; AGND [ADC] = AGND [DAC] = DGND = 0 V; V
BIAS
[ADC] = +5 V;
V
SWING
[ADC] = +2.5 V; f
CLK
= 5 MHz external. All specifications T
MN
to T
MAX1
unless otherwse noted.)
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