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參數資料
| 型號： | AD7776AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 8/12頁 |
| 文件大小： | 220K |
| 代理商： | AD7776AR |
AD7776/AD7777/AD7778
–8–
REV. 0
Microprocessor Interfacing Circuits
T he AD7776/AD7777/AD7778 family of ADCs is intended to
interface to DSP machines such as the ADSP-2101, ADSP-2105,
the T MS320 family and microcontrollers such as the 80C196
family.
Figure 7 shows the AD7776/AD7777/AD7778 interfaced to the
T MS320C10 @ 20.5 MHz and the T MS320C14 @ 25 MHz.
Figure 8 shows the interface with the T MS320C25 @ 40 MHz.
Note that one wait state is required with this interface. T he
ADSP-2101-50 and the ADSP-2105-40 interface is shown in
Figure 9. One wait state is required with either of these machines.
*
ADDITIONAL PINS OMITTED FOR CLARITY
ADDR
DECODE
ADDRESS BUS
DATA BUS
D15–D0
TMS320C10-20.5
TMS320C14-25
A11–A0
WE
(C10) DEN
(C14) REN
CS
AD7776/7/8*
DB9–DB0
RD
WR
Figure 7. AD7776/AD7777/AD7778 to TMS320C10 and
TMS320C14 Interface
ADDRESS BUS
DATA BUS
*
ADDITIONAL PINS OMITTED FOR CLARITY
CS
AD7776/7/8*
DB9–DB0
RD
WR
ADDR
DECODE
D15–D0
A15–A0
IS
READY
MSC
STRB
R/W
TMS320C25-40
Figure 8. AD7776/AD7777/AD7778 to TMS320C25 Interface
Figure 10 shows the interface with the 80C196K B @ 12 MHz
and the 80C196K C @ 16 MHz. One wait state is required with
the 16 MHz machine. T he 80C196 is configured to operate
with a 16-bit multiplexed address/data bus.
T able I gives a truth table for the AD7776/AD7777/AD7778
and summarizes their microprocessor interfacing features. Note
that a read instruction to any of the devices while a conversation
is in progress will immediately stop that conversion and return
unreliable data over the data bus.
*
ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
DATA BUS
CS
AD7776/7/8*
DB9–DB0
RD
WR
D23–D6
A13–A0
WR
RD
DMS
ADSP-2101-50
ADSP-2105-40
ADDR
DECODE
EN
Figure 9. AD7776/AD7777/AD7778 to ADSP-2101 and
ADSP-2105 Interface
*
ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS (10)
CS
DB9–DB0
AD7776/7/8*
RD
WR
ADDR
DECODER
'373
LATCH
ADDRESS BUS
AD7–AD0
(PORT 3)
AD15–AD6
(PORT 4)
WR
RD
80C196KB-12
80C196KC-16
ALE
Figure 10. AD7776/AD7777/AD7778 to 80C196 Interface
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