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參數(shù)資料
| 型號(hào)： | AD7783BRU-REEL |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | Read-Only, Pin Configured 24-Bit ADC with Excitation Current Sources |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MS-153-AB, TSSOP-16 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大小： | 217K |
| 代理商： | AD7783BRU-REEL |
REV. B
–6–
AD7783
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
XTAL1
AD7783
REFIN(+)
REFIN(–)
AIN(+)
AIN(–)
IOUT1
IOUT2
IPIN
XTAL2
V
DD
GND
MODE
DOUT/
RDY
CS
SCLK
RANGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
2
XTAL1
REFIN(+)
Input to the 32.768 kHz Crystal Oscillator Inverter.
Positive Reference Input. REFIN(+) can lie anywhere between V
DD
and GND + 1 V. The nominal refer-
ence voltage (REFIN(+)
–
REFIN(
–
)) is 2.5 V, but the part functions with a reference from 1 V to V
DD
.
Negative Reference Input. This reference input can lie anywhere between GND and V
DD
–
1 V.
Analog Input. AIN(+) is the positive terminal of the fully differential analog input pair AIN(+)/AIN(
–
).
Analog Input. AIN(
–
) is the negative terminal of the fully differential analog input pair AIN(+)/AIN(
–
).
Output from Internal 200
m
A Excitation Current Source. Either current source IEXC1 or IEXC2 can be
switched to this output using hardware control pin IPIN.
Output from Internal 200
m
A Excitation Current Source. Either current source IEXC1 or IEXC2 can be
switched to this output using hardware control pin IPIN.
Logic Input that Selects the Routing of the On-Chip Current Sources. When IPIN is tied to GND, IEXC1
is routed to IOUT1 and IEXC2 is routed to IOUT2. When IPIN is tied to V
DD
, IEXC1 is routed to
IOUT2 and IEXC2 is routed to IOUT1.
Logic Input that Configures the Input Range on the Internal PGA. With RANGE = 0, the full-scale input
range is
±
160 mV; the full-scale input range equals
±
2.56 V when RANGE = 1 for a 2.5 V reference.
Serial Clock Input/Output for Data Transfers from the ADC. When the device is operated in master mode,
SCLK is an output with one SCLK period equal to one XTAL period. In slave mode, SCLK is generated
by an external source. In slave mode, all the data can be transmitted on a continuous train of pulses. Alter-
natively, it can be a noncontinuous clock with the information being transmitted from the AD7783 in
smaller batches of data. SCLK is Schmitt triggered (slave mode), making the interface suitable for opto-
isolated applications.
Chip Select Input.
CS
is an active low logic input used to select the AD7783. When
CS
is low, the PLL
establishes lock and allows the AD7783 to initiate a conversion. When
CS
is high, the conversion is aborted,
DOUT and SCLK are three-stated, the AD7783 enters standby mode, and any conversion result in the
output shift register is lost.
DOUT/
RDY
Serial Data Output/Data Ready Output. DOUT/
RDY
serves a dual purpose in this interface. When a conver-
sion is initiated, DOUT/
RDY
goes high and remains high until the conversion is complete. DOUT/
RDY
will
then return low to indicate that valid data is available to be read from the device. In slave mode, this acts as
an interrupt to the processor, indicating that valid data is available. If data is not read after a conversion,
DOUT/
RDY
will go high before the next update occurs. In master mode, DOUT/
RDY
goes low for at
least half an SCLK cycle before the device produces SCLKs. When SCLK becomes active, data is output
on the DOUT/
RDY
pin. Data is output on the falling SCLK edge and is valid on the rising edge.
MODE
The MODE pin selects master or slave mode of operation. When MODE = 0, the AD7783 operates in
master mode; the AD7783 is configured for slave mode when MODE = 1.
GND
Ground Reference Point for the AD7783.
V
DD
Supply Voltage, 3 V or 5 V Nominal.
XTAL2
Output from the 32.768 kHz Crystal Oscillator Inverter.
3
4
5
6
REFIN(
–
)
AIN(+)
AIN(
–
)
IOUT1
7
IOUT2
8
IPIN
9
RANGE
10
SCLK
11
CS
12
13
14
15
16
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